Inovance MD500T75G - Page 268

9. Peripherals and Options MD500 User Manual
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0'3*0'3*'7HUPLQDOV
'%7HUPLQDO1R Mark Description
1 A+ Encoder output signal A positive
2 A- Encoder output signal A negative
3 B+ Encoder output signal B positive
4 B- Encoder output signal B negative
5 Z+ Encoder output signal Z positive
6 Null -
7 +5V Encoder 5V power supply positive
8 COM Encoder power supply negative
 Z- Encoder output signal Z negative
User interfaces J7, J8: MD38PG6
has the 1:1 frequency dividing
output. MD38PG6D has the
selectable frequency dividing
output (1:4 by default).
A+ Frequency dividing output signal A positive
A- Frequency dividing output signal A negative
B+ Frequency dividing output signal B positive
B- Frequency dividing output signal B negative
Z+ Frequency dividing output signal Z positive
Z- Frequency dividing output signal Z negative
COM Signal power ground
PE Shield connecting point
Ƶ
'HVFULSWLRQRI)UHTXHQF\'LYLGLQJRI0'3*'0'3*'
7KHIUHTXHQF\GLYLGLQJFRHIÀFLHQWLVGHWHUPLQHGE\WKH',3VZLWFK.RQWKH3*FDUG7KH',3VZLWFKKDVDWRWDORIÀYHGLJLWV
7KHFRHIÀFLHQWLVREWDLQHGE\PXOWLSO\LQJWKHELQDU\QXPEHUH[SUHVVHGE\WKH',3VZLWFKE\%LWLVWKHORZHVWELWDQGELWLV
the highest bit. If the bit is set to ON, it is effective. Minimum 1:4 and maximum 1:62 frequency dividing can be implemented.
7KHFRUUHVSRQGHQFHRIWKHELQDU\QXPEHUH[SUHVVHGE\WKH',3VZLWFKDQGWKHIUHTXHQF\GLYLGLQJFRHIÀFLHQWLVDVOLVWHGLQWKH
following table.
Binary Number )UHTXHQF\'LYLGLQJ&RHIÀFLHQW
0 00000 No output
1 00001 No output
2 00010 22
………
iii x 2
………
31 11111 31 x 2
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