Intel Agilex

Figure 6. Data Input Registers in Fixed-Point Arithmetic 9 x 9 Mode
ay[8..0]
ax[8..0]
by[8..0]
CLK
ENA[2..0]
CLR[0]
by[8..0]
cy[8..0]
cx[8..0]
dy[8..0]
dx[8..0]
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Intel
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Variable Precision DSP Blocks User Guide
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