Intel Agilex User Guide

Related Information
Configurations for Input, Pipeline, and Output Registers on page 67
Provides information about restrictions on floating-point arithmetic input registers.
2.2.2. Pipeline Registers for Floating-Point Arithmetic
Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all
latency layers of the pipeline registers or use any one, two or three layers of pipeline
registers.
Figure 12. Location of Pipeline Register for FP32 Operation Modes
fp32_chainout[31:0]
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
1
2
fp32_result[31:0]
Input
Register
Bank
Multiplier
Adder
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Output
Register
Bank
fp32_mult_a[31:0]
fp32_mult_b[31:0]
3
4
5
6
Legend:
1 - accum_pipeline_clken
2 - fp32_adder_a_chainin_pl_clken
3 - accum_2nd_pipeline_clken
4 - fp32_adder_a_chainin_2nd_pl_clken
5 - accum_adder_clken
6 - adder_input_clken
7 - fp32_mult_b_clken
8 - mult_2nd_pipeline_clken
6
8
7
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Intel
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Variable Precision DSP Blocks User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English