Intel Agilex User Guide

2.2.4. Adder or Subtractor for Floating-Point Arithmetic
Depending on the operational mode, you can use the adder or subtractor as
• A single precision addition/subtraction
• A single-precision multiplication with addition/subtraction
• Summation/subtraction of two half-precision multiplications with single precision
result
• Summation/subtraction of two half-precision multiplications and addition/
subtraction with single precision result
• Summation/subtraction of two half-precision multiplications accumulated into a
single precision result
2.2.5. Output Register Bank for Floating-Point Arithmetic
The positive edge of the clock signal triggers the 48-bit (32 bits data and 16 bits
exception flags) bypassable output register bank and is cleared after power up.
Figure 14. Location of Output Register for FP32 Operation Modes
fp32_chainout[31:0]
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
fp32_result[31:0]
Multiplier
Adder
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
*Pipeline
Register
output_clken
fp32_mult_a[31:0]
fp32_mult_b[31:0]
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
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Variable Precision DSP Blocks User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English