Intel Agilex User Guide

Operation Mode Register Level Input Register Pipeline Register 2nd Pipeline
Register
Output Register
18 x 19 systolic
mode
2 Enable Disable Disable Enable
3
(6)
Enable Enable Disable Enable
3
(7)
Enable Disable Enable Enable
4 Enable Enable Enable Enable
Independent
27 x 27
multiplication
0 Disable Disable Disable Disable
1 Enable Disable Disable Disable
1
(5)
Disable Disable Disable Enable
2 Enable Disable Disable Enable
3
(6)
Enable Enable Disable Enable
3
(7)
Enable Disable Enable Enable
4 Enable Enable Enable Enable
4.1.2. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic
In both 18-bit and 27-bit modes, you can use the coefficient feature and pre-adder
feature independently.
When pre-adder feature is enabled in 18-bit modes, you must enable both top and
bottom pre-adder.
When internal coefficient feature is enabled in 18-bit modes, you must enable both top
and bottom coefficient.
4.1.3. Accumulator for Fixed-Point Arithmetic
The accumulator in the Intel Agilex devices supports double accumulation by enabling
the 64-bit double accumulation registers located between the output register bank and
the accumulator.
4.1.4. Input Cascade for Fixed-Point Arithmetic
The input register bank in Intel Agilex variable precision DSP block supports input
cascade feature. This feature provides the capability of cascading the input bus within
a DSP block and to another DSP block.
When you enable the input cascade feature in 18 x 19 mode:
• The top multiplier Y input drives the bottom multiplier Y input within a DSP block
• The bottom multiplier Y input of the first DSP block drives the top multiplier Y
input of the subsequent DSP block
For 27 × 27 mode, the multiplier Y input of the first DSP block drives the multiplier Y
input of the subsequent DSP block. This feature is not supported with pre-adder
enabled.
There are two delay registers that you can use to balance the latency requirements
when you use both the input cascade and chainout features in fixed-point arithmetic
18 x 19 mode. These are the top delay registers and bottom delay registers. The ay
4. Intel Agilex Variable Precision DSP Blocks Design Considerations
UG-20213 | 2019.04.02
Intel
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Variable Precision DSP Blocks User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English