Intel Agilex User Guide

Figure 9. Dynamic Chainout
disable_chainout
64’b0
chainout
0
1
Input
register
Output
register
Table 8. DISABLE_CHAINOUT Signal Behavior
DISABLE_CHAINOUT Signal Description
Low (0) Chainout = result from output register
High (1) Chainout = 0. Chainin to the next variable precision DSP
block is disabled.
2.1.8. Systolic Register for Fixed-Point Arithmetic
There are two sets of systolic registers per variable precision DSP block and each set
supports up to 44 bits chain in and chain out adder. If the variable precision DSP block
is not configured in fixed-point arithmetic systolic FIR mode, both sets of systolic
registers are bypassed.
The first set of systolic registers consists of 18-bit and 19-bit registers that are used to
register the 18-bit and 19-bit inputs of the upper multiplier, respectively.
The second set of systolic registers are used to delay the chainin input from the
previous variable precision DSP block.
Below are the guidelines when implementing systolic registers in your design:
• The input and output register must be enabled when using systolic registers.
• First and second pipeline registers are optional when using systolic registers. If
second pipeline is enabled, use the same clock enable as the input systolic
register.
• The chainin systolic register always has the same clock enable as the output
register.
2.1.9. Double Accumulation Register for Fixed-Point Arithmetic
The accumulator supports double accumulation by enabling the 64-bit double
accumulation registers located between the output register bank and the accumulator
feedback path.
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Send Feedback
Intel
®
Agilex
™
Variable Precision DSP Blocks User Guide
19

Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English