Name: Intel Agilex
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Figure 4. Floating-Point Arithmetic 16-bit Half-Precision Mode

fp32_chainout[31:0]

fp32_chainin[31:0]

accumulate

fp32_adder_a[31:0]

fp16_mult_top_a[15:0]

fp32_result[31:0]

Input

Bank

Top

Multiplier

Adder

*Pipeline

Output

Bank

*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.

fp16_mult_top_b[15:0]

fp16_mult_bot_a[15:0]

Bottom

Multiplier

fp16_mult_bot_b[15:0]

*Pipeline

Adder

fp16_mult_top_invalid

fp16_mult_top_underflow

fp16_mult_top_overflow

fp32_adder_invalid

fp32_adder_inexact

fp32_adder_overflow

fp32_adder_underflow

fp16_mult_top_inexact

fp16_mult_bot_invalid

fp16_mult_bot_underflow

fp16_mult_bot_overflow

fp16_mult_bot_inexact

fp16_adder_invalid

fp16_adder_inexact

fp16_adder_overflow

fp16_adder_underflow

fp16_mult_top_infinite

fp16_mult_top_zero

fp16_mult_bot_infinite

fp16_mult_top_zero

fp16_adder_infinite

fp16_adder_zero

Figure 5. Floating-Point Arithmetic 32-bit Single-Precision Mode

fp32_chainout[31:0]

fp32_chainin[31:0]

accumulate

fp32_adder_a[31:0]

fp32_adder_b[31:0]

fp32_result[31:0]

Input

Bank

Multiplier

Adder

*Pipeline

fp32_mult_invalid

fp32_mult_inexact

fp32_mult_overflow

fp32_mult_underflow

fp32_adder_invalid

fp32_adder_inexact

fp32_adder_overflow

fp32_adder_underflow

*Pipeline

Output

Bank

*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.

fp32_mult_a[31:0]

fp32_mult_b[31:0]

2.1. Fixed-Point Arithmetic

2.1.1. Input Register Bank for Fixed-Point Arithmetic

The input register banks for fixed-point DSP blocks are available for the following input

signals:

2. Intel Agilex Variable Precision DSP Blocks Architecture

UG-20213 | 2019.04.02

Intel

Agilex

™

Variable Precision DSP Blocks User Guide