Intel Agilex User Guide

4. Intel Agilex Variable Precision DSP Blocks Design
Considerations
You should consider the following elements in your design:
Table 23. Design Considerations
DSP Functions Design Elements
Fixed-point arithmetic • Operational modes
• Input, pipeline, and output registers
• Internal coefficient and pre-adder
• Accumulator
• Chainout adder
• Input cascade
Floating-point arithmetic • Input, pipeline, and output registers
• Operational modes
• Chainout adder
4.1. Fixed-Point Arithmetic
4.1.1. Configurations for Input, Pipeline, and Output Registers
The configurations for the input, pipeline, and output registers are restricted due to
the timing model in Intel Agilex devices. Therefore these registers only support certain
configurations.
Restrictions for Input Registers
The following are the clock enable restrictions for input registers:
• When using 9 x 9 sum of 4 operational mode, the following input signal pairs must
use the same clock enable settings:
—
ax and bx
—
ay and by
—
cx and dx
—
cy and dy
•
If the input registers for SUB, NEGATE, ACCUMULATE, and LOADCONST signals are
enabled, these registers must use the same clock enable settings.
•
Disable the input registers for SUB, NEGATE, ACCUMULATE, and LOADCONST
signals if these signals are driven by a constant value.
Restrictions for Pipeline Registers
The following are the clock enable restrictions for pipeline registers:
UG-20213 | 2019.04.02
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English