Intel Agilex User Guide

Figure 46. Complex Multiplication with Result Real Using FP16 Half-Precision Floating-
Point Arithmetic
b
d
a
c
Result Real
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
fp32_chainout[31:0]
fp32_chainout[31:0]
fp16_mult_top_a[15:0]
fp32_result[31:0]
Input
Register
Bank
Top
Multiplier
*Pipeline
Register
fp16_mult_top_invalid
fp16_mult_top_underflow
fp16_mult_top_overflow
fp16_adder_invalid
fp16_adder_inexact
*Pipeline
Register
Output
Register
Bank
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
Bottom
Multiplier
fp16_mult_bot_b[15:0]
*Pipeline
Register
Register
Adder
fp16_mult_top_inexact
fp16_mult_bot_invalid
fp16_mult_bot_underflow
fp16_mult_bot_overflow
fp16_mult_bot_inexact
fp16_mult_top_infinite(extended mode)
fp16_mult_top_zero(extended mode)
fp16_mult_bot_infinite(extended mode)
fp16_mult_bot_zero(extended mode)
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Send Feedback
Intel
®
Agilex
™
Variable Precision DSP Blocks User Guide
61

Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English