Figure 15. Location of Output Register for FP16 Operation Modes
fp32_chainout[31:0]
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp16_mult_top_a[15:0]
fp32_result[31:0]
Input
Register
Bank
Top
Multiplier
Adder
fp16_mult_top_invalid
fp16_mult_top_underflow
fp16_mult_top_overflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
output_clken
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
Bottom
Multiplier
fp16_mult_bot_b[15:0]
*Pipeline
Register
Adder
fp16_mult_top_inexact
fp16_mult_bot_invalid
fp16_mult_bot_underflow
fp16_mult_bot_overflow
fp16_mult_bot_inexact
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_mult_top_infinite
fp16_mult_top_zero
fp16_mult_bot_infinite
fp16_mult_top_zero
fp16_adder_zero
fp16_adder_infinite
The following variable precision DSP block signals control the output register per
variable precision DSP block:
•
CLK
•
ENA[2..0]
•
CLR[1]
Related Information
Configurations for Input, Pipeline, and Output Registers on page 67
Provides information about restrictions on floating-point arithmetic output
registers.
2.2.6. Exception Handling for Floating-Point Arithmetic
The Intel Agilex floating-point arithmetic supports exception handling for the multiplier
and adder blocks.
Table 9. Supported Exception Flags
Floating-
Point
Format
Exception Flags Width Description
Single
precision
Multiplication
fp32_mult_overflow
1 This signal indicates if the multiplier result is a larger value than the
maximum presentable value.
1: If the multiplier result is a larger value than the maximum
representable value and the result is cast to infinity.
0: If the multiplier result is not larger than the maximum
presentable value.
This signal is not available in Adder or Subtract Mode.
fp32_mult_underflow
1 This signal indicates if the multiplier result is a smaller value than
the minimum presentable value.
continued...
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
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