Intel Agilex

Figure 7. Data Input Registers in Fixed-Point Arithmetic 18 x 19 Mode
ay[18..0]
az[17..0]
ax[17..0]
by[18..0]
Top delay registers
bz[17..0]
bx[17..0]
Bottom delay registers
scanin[18..0]
scanout[18..0]
CLK
ENA[2..0]
CLR[0]
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
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Variable Precision DSP Blocks User Guide
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