Table 2. Supported Combinations of Operational Modes and Dynamic Control Features
Variable-
Precision
DSP Block
Resource
Operation
Mode
Dynamic
ACCUMULAT
E
Dynamic
LOADCONST
Dynamic
SUB
Dynamic
NEGATE
Dynamic
Scanin
Dynamic
Chainout
1 variable
precision
DSP block
Fixed-point four
9 x9 multiplier
adder mode
Yes Yes No No No Yes
Fixed-point
independent
18 x 19
multiplication
No No No No Yes No
Fixed-point
independent
27 x 27
multiplication
Yes Yes No Yes No Yes
Fixed-point two
18 x 19
multiplier adder
mode
Yes Yes Yes Yes Yes Yes
Fixed-point
18 x 18
multiplier adder
summed with
36-bit input
Yes Yes Yes Yes No Yes
Fixed-point
18 x 19 systolic
mode
Yes Yes Yes Yes Yes Yes
2 variable
precision
DSP blocks
Fixed-point
complex
18 x 19
multiplication
No No No No No No
Related Information
• Intel Agilex Device Overview—Intel Agilex FPGAs Family Plan
Refer to the Intel Agilex FPGAs Family Plan in the Intel Agilex Device Overview
for more information on the variable precision DSP blocks resources.
• Pre-adder for Fixed-Point Arithmetic on page 17
• Internal Coefficient for Fixed-Point Arithmetic on page 17
• Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic on
page 18
• Input Cascade for Fixed-Point Arithmetic on page 64
• Intel Agilex Variable Precision DSP Blocks Design Considerations on page 62
1. Intel
®
Agilex
™
Variable Precision DSP Blocks Overview
UG-20213 | 2019.04.02
Intel
®
Agilex
™
Variable Precision DSP Blocks User Guide
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