Electrical
Design Guide 21
NOTES:
1. Value in the Legacy column list timings for power supplies designed before the year
2020. In 2020, the T1 and T3 timings have moved from the Legacy timing to the new
Required column for all new power supply designs.
2. T3 minimum must not be faster than 100ms especially for previous generation
motherboards and systems. All design tolerances must be considered to avoid T3 faster
than 100ms.
a. A T3 time less than 100ms may be designed based on system requirements
and a need to provide faster PSU and system turn on capability. However,
PSU and system designers are highly recommended to verify and ensure no
PSU and system compatibility problems exist, especially for previous
generation motherboards and systems.
3. T5 to be defined for both max/min load condition.
4. PSUs are recommended to label or indicate the timing value for system designer and
integrator reference for T1 and T3. This allows system designers to optimize “turn on”
time within the system.
3.3.1 PWR_OK – Required
PWR_OK is a “power good” signal. This signal shall be asserted high by the power
supply to indicate that the +12 VDC, +5 VDC, and +3.3 VDC outputs are within the
regulation thresholds listed in Table 3-2
and that sufficient mains energy is stored by
the converter to guarantee continuous power operation within the specification for at
least the duration specified in Section
3.2.9. Conversely, PWR_OK should be de-
asserted to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output
voltages falls below its voltage threshold, or when mains power has been removed for
a time sufficiently long enough, such that power supply operation cannot be
guaranteed. The electrical and timing characteristics of the PWR_OK signal are given
in
Table 3-9.
PSU manufacturers are required to label or tag PSU DG revision compliance to
reflect the timing supported.
Table 3-9: PWR_OK Signal Characteristics
Signal Type
+5 V TTL compatible
Logic Level Low
< 0.4 V while sinking 4 mA
Logic Level High
Between 2.4 V and 5 V output while sourcing 200 μA
High State Output Impedance
1 kΩ from output to common
Max Ripple/Noise
400 mV p-p
3.3.2 Power-Up Cross Loading Condition – Required
In the time frame between PS_ON# assertion and PWR_OK assertion (T1+T3), the
power supply may be subjected to a cross load condition on the 12 V, 3.3 V and 5 V
rails. The power supply must be able to successfully power-up and assert PWR_OK
when 12 V (or combination of 12V1 and 12V2) is loaded to ≤ 0.1 A and 3.3 V and/or 5
V are loaded to 0-5 A.
To Next Page
Loading...
Need help?
General
