Design Guide 7
Revision History
Document
Number
Revision
Number
Description Revision Date
336521
001
• Initial Release
September, 2017
002
• Updated Table 2-1
: 12V2 Current for Processor
Configurations.
• Updated Figure 3: Power Supply Timing.
• Added Figure 5: +5VSB Power on timing versus VAC.
• Added note Table 4-8: +3.3V is removed from SATA
V3.2 spec.
• Updated Chapter 10:
− CFX12V Specific Guidelines to version 1.62
− LFX12V Specific Guidelines to version 1.42
− ATX12V Specific Guidelines to version 2.52
− SFX12V Specific Guidelines to version 3.42
− TFX12V Specific Guidelines to version 2.52
− Flex ATX Specific Guidelines to version 1.22
• Removed Chapter 16 test plan. Refer to Document
#595284
for test plan.
• Added Section 9.2. Reliability – PS_ON# toggle for S0ix
mode.
June, 2018
003
• Added Section 1.1
Alternative Low Power Mode for
Power Supplies.
• Updated Table 2-1: 12V2 Current for 10th Gen Intel
®
Core
TM
Processor Configurations.
• Added PSU Addendum for all future processor support
in Section 2.1.
• Update Table 3-4: 5VSB efficiency
• Updated Table 3-6: -12VDC capacitive load from
3300uF to 330uF.
• Updated Section 3.5.8 and added Table 3-13.
• Updated Section 3.5.9 to support Energy Star v8.
• Updated Section 4.3.2 for PS_ON# is asserted.
• Updated Section 9.2 Reliability – PS_ON# toggle for
S0ix mode.
• Updated Chapter 10-15:
− CFX12V Specific Guidelines to version 1.63
− LFX12V Specific Guidelines to version 1.43
− ATX12V Specific Guidelines to version 2.53
− SFX12V Specific Guidelines to version 3.43
− TFX12V Specific Guidelines to version 2.53
− Flex ATX Specific Guidelines to version 1.23
June, 2020
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