Electrical
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Parameter Description
Value
Required Recommended
T2 Rise time 0.2–20 ms
T3 PWR_OK delay
3
1ms – 150ms
1
1–100 ms
T4 PWR_OK rise time < 10 ms
T5
AC loss to PWR_OK
hold-up time
3
> 16 ms
2
T6
PWR_OK inactive to
DC loss delay
> 1 ms
NOTES:
T1 and T3 required values are set to meet timing requirement for computers that use
ALPM.
T5 to be defined for both max/min load condition.
PSUs are recommended to label or indicate the timing value for system designer and
integrator reference for T1 and T3. This allows system designers to optimize “turn on”
time within the system.
T0 is shown in Section 4.3.3, Figure 4-4.
4.3.1 PWR_OK (Required)
PWR_OK is a “power good” signal. This signal shall be asserted high by the power
supply to indicate that the +12 VDC outputs are within the regulation thresholds listed
in Table 4-2
and that sufficient mains energy is stored by the converter to guarantee
continuous power operation within the specification for at least the duration specified
in Section
4.2.9. Conversely, PWR_OK shall be de-asserted to a low state when any of
the +12 VDC output voltages fall below its voltage threshold, or when mains power
has been removed for a time sufficiently long enough, such that power supply
operation cannot be guaranteed. The electrical and timing characteristics of the
PWR_OK signal is given in the below table.
Table 4-9: PWR_OK Signal Characteristics
Signal Type
+5 V TTL compatible
Logic level Low
< 0.4 V while sinking 4 mA
Logic level High
Between 2.4 V and 5 V output while sourcing 200 μA
High State Output Impedance
1 kΩ from output to common
Max Ripple/Noise
400 mV p-p
4.3.2 PS_ON# (Required)
PS_ON# is an active-low, TTL-compatible signal that allows a motherboard to
remotely control the power supply in conjunction with features such as soft on/off,
Wake on LAN, or wake-on-modem. When PS_ON# is pulled to TTL low, the power
supply shall turn on the main DC output rail: +12 VDC. When PS_ON# is pulled to TTL
high or open-circuited, the DC output rails should not deliver current and should be
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