Intel CELERON 1.10 GHZ - Power-On Reset and Configuration Timings; Test Timings (TAP Connection); Test Reset Timings

Datasheet 51
Intel
®
Celeron
®
Processor up to 1.10 GHz
Figure 8. Power-On Reset and Configuration Timings
Figure 9. Test Timings (TAP Connection)
Figure 10. Test Reset Timings
T
a
Valid Ratio
T
C
T
b
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
INTR, NMI)
T
a
= T15 (PWRGOOD Inactive Pulse)
T
b
= T10 (RESET# Pulse Width)
T
c
= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA)
BCLK
V
IL, max
V
IH, min
Vcc
CORE
, V
TT
,
V
REF
TCK
T
DI, TMS
Input
Signals
TDO
Output
Signals
1.25V
T
v
T
w
T
r
T
s
T
x
T
u
T
y
T
z
1.25V
T
r
T43 (All Non-Test Inputs Setup Time)=
T
s
T44 (All Non-Test Inputs Hold Time)=
T
u
T40 (TDO Float Delay)=
T
v
T37 (TDI, TMS Setup Time)=
T
w
T38 (TDI, TMS Hold Time)=
T
x
T39 (TDO Valid Delay)=
T
y
T41 (All Non-Test Outputs Valid Delay)=
T
z
T42 (All Non-Test Outputs Float Delay)=
TRST#
C
1.25V
T
q
T
q
T37 (TRST# Pulse Width)=