86 Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
N37 Reserved Reserved for Future Use
P2 V
CC
CORE
Power/Other
P4 D18# AGTL+ I/O
P6 D9# AGTL+ I/O
P32 V
SS Power/Other
P34 V
CC
CORE
Power/Other
P36 V
SS Power/Other
Q1 D12# AGTL+ I/O
Q3 D10# AGTL+ I/O
Q5 V
SS Power/Other
Q33 Reserved Reserved for Future Use
Q35 Reserved Reserved for Future Use
Q37 Reserved Reserved for Future Use
R2 Reserved Reserved for Future Use
R4 D17# AGTL+ I/O
R6 V
REF3 Power/Other
R32 V
CC
CORE
Power/Other
R34 V
SS Power/Other
R36 V
CC
CORE
Power/Other
S1 D8# AGTL+ I/O
S3 D5# AGTL+ I/O
S5 V
CC
CORE
Power/Other
S33 Reserved Reserved for Future Use
S35 Reserved Reserved for Future Use
S37 Reserved Reserved for Future Use
T2 V
CC
CORE
Power/Other
T4 D1# AGTL+ I/O
T6 D6# AGTL+ I/O
T32 V
SS Power/Other
T34 V
CC
CORE
Power/Other
T36 V
SS Power/Other
U1 D4# AGTL+ I/O
U3 D15# AGTL+ I/O
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
U5 VSS Power/Other
U33 PLL2 Power/Other
U35 Reserved Reserved for Future Use
U37 Reserved Reserved for Future Use
V2 V
SS Power/Other
V4 Reserved Reserved for Future Use
V6 V
REF4 Power/Other
V32 V
CC
CORE
Power/Other
V34 V
SS Power/Other
V36 V
CC
CORE
Power/Other
W1 D0# AGTL+ I/O
W3 Reserved Reserved for Future Use
W5 V
CC
CORE
Power/Other
W33 PLL1 Power/Other
W35 Reserved Reserved for Future Use
W37 BCLK System Bus Clock Input
X2 Reserved Reserved for Future Use
X4 RESET# AGTL+ Input
X6 Reserved Reserved for Future Use
X32 V
SS Power/Other
X34 V
CC
CORE
Power/Other
X36 V
SS Power/Other
Y1 Reserved Reserved for Future Use
Y3 A26# AGTL+ I/O
Y5 V
SS Power/Other
Y33 V
SS Power/Other
Y35 V
CC
CORE
Power/Other
Y37 V
SS Power/Other
Z2 V
SS Power/Other
Z4 A29# AGTL+ I/O
Z6 A18# AGTL+ I/O
Z32 V
CC
CORE
Power/Other
Z34 V
SS Power/Other
Z36 V
CC
2.5
Power/Other
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No. Pin Name Signal Buffer Type
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