Intel CELERON 1.10 GHZ - Table of Contents

Datasheet 3
Intel
®
Celeron
®
Processor up to 1.10 GHz
Contents
1.0 Introduction.......................................................................................................................11
1.1 Terminology.........................................................................................................11
1.1.1 Package Terminology.............................................................................12
1.1.2 Processor Naming Convention...............................................................13
1.2 References..........................................................................................................14
2.0 Electrical Specifications....................................................................................................15
2.1 System Bus and Vref...........................................................................................15
2.2 Clock Control and Low Power States..................................................................15
2.2.1 Normal State—State 1 ...........................................................................16
2.2.2 AutoHALT Power Down State—State 2 .................................................16
2.2.3 Stop-Grant State—State 3 .....................................................................17
2.2.4 HALT/Grant Snoop State—State 4 ........................................................17
2.2.5 Sleep State—State 5..............................................................................17
2.2.6 Deep Sleep State—State 6 ....................................................................18
2.2.7 Clock Control..........................................................................................18
2.3 Power and Ground Pins ......................................................................................18
2.3.1 Phase Lock Loop (PLL) Power...............................................................19
2.4 Processor Decoupling .........................................................................................19
2.4.1 System Bus AGTL+ Decoupling.............................................................19
2.5 Voltage Identification...........................................................................................20
2.6 System Bus Unused Pins....................................................................................21
2.7 Processor System Bus Signal Groups ................................................................21
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals ......................23
2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................23
2.8 Test Access Port (TAP) Connection....................................................................23
2.9 Maximum Ratings................................................................................................23
2.10 Processor DC Specifications...............................................................................24
2.11 AGTL+ System Bus Specifications .....................................................................33
2.12 System Bus AC Specifications............................................................................34
3.0 System Bus Signal Simulations........................................................................................52
3.1 System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................52
3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55
3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57
3.3.1 Overshoot/Undershoot Guidelines .........................................................57
3.3.2 Ringback Specification...........................................................................58
3.3.3 Settling Limit Guideline...........................................................................59
3.4 AGTL+ Signal Quality Specifications and Measurement Guidelines
(FC-PGA/FC-PGA2 Packages)...........................................................................59
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages).......59
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages).......59
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2
Packages) ..............................................................................................60
3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) ......................................60