Intel CELERON 1.10 GHZ - Side View Space Requirements for the Boxed Processor in the S.E

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Datasheet 111

Intel

Celeron

Processor up to 1.10 GHz

Figure 31. Retention Mechanism for the Boxed Intel

Celeron

Processor in the S.E.P.

Package

Figure 32.

Side View Space Requirements for the Boxed Processor in the S.E.P.

Package

242-Contact Slot Connector

Fan Heatsink

S.E.P.P.

1.386

(A)

0.576 (B)

Main Page

Table of Contents3
Revision History9
Introduction11
- Terminology11
  - Package Terminology12
  - Processor Naming Convention13
- Processor Identification13
- References14
Electrical Specifications15
- System Bus and Vref15
- Clock Control and Low Power States15
  - Normal State-State 116
  - Autohalt Power down State-State 216
- Clock Control State Machine16
  - Stop-Grant State-State 317
  - Halt/Grant Snoop State-State 417
  - Sleep State-State 517
  - Deep Sleep State-State 618
  - Clock Control18
- Power and Ground Pins18
  - Phase Lock Loop (PLL) Power19
- Processor Decoupling19
  - System Bus AGTL+ Decoupling19
  - Package19
- Voltage Identification20
- Voltage Identification Definition20
- System Bus Unused Pins21
- Processor System Bus Signal Groups21
- Intel ® Celeron ® Processor System Bus Signal Groups22
  - Asynchronous Vs. Synchronous for System Bus Signals23
  - System Bus Frequency Select Signal (BSEL[1:0])23
- Test Access Port (TAP) Connection23
- Maximum Ratings23
- Processor DC Specifications24
- Absolute Maximum Ratings24
- Voltage and Current Specifications25
- AGTL+ Signal Groups DC Specifications31
- Non-AGTL+ Signal Group DC Specifications32
- AGTL+ System Bus Specifications33
- Processor AGTL+ Bus Specifications33
- System Bus AC Specifications34
- System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E35
- System Bus AC Specifications (Clock) at the Processor Core Pins (for both S.E.P. and PGA Packages)36
- Valid Intel ® Celeron ® Processor System Bus, Core Frequency38
- System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S.E39
- System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for S.E39
- Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for PPGA Package)40
- System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for FC-PGA/FC-PGA2 Packages)40
- System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E41
- System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)41
- System Bus AC Specifications (CMOS Signal Group)42
- System Bus AC Specifications (Reset Conditions) (for both S.E.P. and PPGA Packages)42
- System Bus AC Specifications (Reset Conditions)42
- System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (for S.E43
- System Bus AC Specifications (APIC Clock and APIC I/O)43
- System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (for S.E.P. and PGA Packages)44
- System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (for S.E45
- System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for both S.E.P. and PPGA Packages)46
- System Bus AC Specifications (TAP Connection)47
- BCLK to Core Logic Offset48
- BCLK*, PICCLK, and TCK Generic Clock Waveform49
- System Bus Valid Delay Timings49
- System Bus Setup and Hold Timings49
- System Bus Reset and Configuration Timings (for the S.E.P. and PPGA Packages)50
- System Bus Reset and Configuration Timings (for the FC-PGA/FC-PGA2 Package)50
- Power-On Reset and Configuration Timings51
- Test Timings (TAP Connection)51
- Test Reset Timings51
System Bus Signal Simulations52
- System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines52
- BCLK Signal Quality Specifications for Simulation at the Processor Core (for both S.E.P. and PPGA Packages)52
- BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins53
- BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the FC-PGA/FC-PGA2 Packages)53
- BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers54
- BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E54
- AGTL+ Signal Quality Specifications and Measurement Guidelines55
- AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (for both the S.E.P. and PPGA Packages)55
AGTL+ Signal Groups Ringback Tolerance Specifications at the55
- Processor Pins (for FC-PGA/FC-PGA2 Packages)55
- Low to High AGTL+ Receiver Ringback Tolerance56
AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E56
- Non-AGTL+ Signal Quality Specifications and Measurement Guidelines57
  - Overshoot/Undershoot Guidelines57
- Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback57
  - Ringback Specification58
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S.E.P. and PPGA Packages)58
Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E58
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (FC-PGA/FC-PGA2 Packages)58
- Settling Limit Guideline59
- AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages)59
Example Platform Information61
- Determining if a System Meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packages)62
- Mhz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages)62
- Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages)63
- Mhz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages)63
- Non-AGTL+ Signal Quality Specifications and Measurement Guidelines64
- Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback64
Thermal Specifications and Design Considerations65
- Thermal Specifications65
Processor Power for the PPGA and FC-PGA Packages66
- Processor Functional die Layout (CPUID 0686H)67
- Processor Functional die Layout (up to CPUID 0683H)67
  - Thermal Diode68
Thermal Diode Parameters (S.E.P. and PPGA Packages)68
Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)68
Thermal Diode Interface68
Mechanical Specifications69
- Package69
  - Materials Information69
  - Signal Listing (S.E70
- Processor Substrate Dimensions (S.E70
- Processor Substrate Primary/Secondary Side Dimensions (S.E70
S.E.P. Package Signal Listing by Pin Number71
S.E.P. Package Signal Listing by Signal Name75
- PPGA Package79
  - PPGA Package Materials Information79
- Package Dimensions (PPGA Package)79
Package Dimensions (PPGA Package)80
Information Summary (PPGA Package)80
- PPGA Package Signal Listing81
- PPGA Package (Pin Side View)81
PPGA Package Signal Listing by Pin Number86
PPGA Package Signal Listing in Order by Signal Name88
- FC-PGA/FC-PGA2 Packages92
  - FC-PGA/FC-PGA2 Packages)92
  - FC-PGA Mechanical Specifications92
- Package Dimensions (FC-PGA Package)92
Package Dimensions (FC-PGA Package)93
Processor die Loading Parameters (FC-PGA Package)93
- Mechanical Specifications (FC-PGA2 Package)94
- Package Dimensions (FC-PGA2 Package)94
Package Dimensions (FC-PGA2 Package)95
Processor Case Loading Parameters (FC-PGA2 Package)95
- Recommended Mechanical Keep-Out Zones (FC-PGA2 Package)96
- Volumetric Keep-Out96
- Component Keep-Out96
  - FC-PGA/FC-PGA2 Package Signal List97
- Package Dimensions (FC-PGA/FC-PGA2 Packages)97
FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name98
FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number107
- Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)108
- Top Side Processor Markings (PPGA Package)108
- Top Side Processor Markings (FC-PGA Package)108
- Top Side Processor Markings (FC-PGA2 Package)108
- Heatsink Volumetric Keepout Zone Guidelines109
Boxed Processor Specifications110
- Mechanical Specifications for the Boxed Intel110
  - Celeron ® Processor110
  - Mechanical Specifications for the S.E110
- Side View Space Requirements for the Boxed Processor in the S.E111
  - Boxed Processor Heatsink Weight112
  - Boxed Processor Retention Mechanism112
- Front View Space Requirements for the Boxed Processor in the S.E112
Boxed Processor Fan Heatsink Spatial Dimensions for the S.E112
- Mechanical Specifications for the PPGA Package113
- Side View Space Requirements for the Boxed Processor in the PPGA Package113
  - Boxed Processor Heatsink Weight114
  - Mechanical Specifications for the FC-PGA/FC-PGA2 Packages114
- Conceptual Drawing of the Boxed Intel114
- Dimensions of Mechanical Step Feature in Heatsink Base for the114
  - FC-PGA/FC-PGA2 Packages114
    - Boxed Processor Heatsink Weight115
- Thermal Specifications115
  - Thermal Requirements for the Boxed Intel115
    - Celeron ® Processor115
    - Boxed Processor Cooling Requirements115
- Top View Airspace Requirements for the Boxed Processor in the S.E115
Side View Airspace Requirements for the Boxed Intel116
Volumetric Keepout Requirements for the Boxed Fan Heatsink116
- Boxed Processor Thermal Cooling Solution Clip117
- Electrical Requirements for the Boxed Intel117
  - Electrical Requirements117
Clip Keepout Requirements for the 370-Pin (Top View)117
Boxed Processor Fan Heatsink Power Cable Connector Description118
Fan Heatsink Power and Signal Specifications118
Motherboard Power Header Placement for the S.E119
Motherboard Power Header Placement Relative to the 370-Pin Socket119
Alphabetical Signal Reference120
- Signal Summaries126
Processor Signal Description120
Output Signals126
Input Signals127
Input/Output Signals (Single Driver)128
Input/Output Signals (Multiple Driver)128

Intel CELERON 1.10 GHZ - Side View Space Requirements for the Boxed Processor in the S.E

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