GUIDELINE: Ensure your design includes the necessary Quartus settings to
configure the HPS EMAC outputs for the required delays.
On the Cyclone V/Arria V SoC Development Kit and the associated Golden Hardware
Reference Design (the GHRD is the hardware component of the GSRD) PHY skew is
implemented with the Microchip* (Micrel*) KSZ9021RN PHY. Refer to the
hps_common_board_info.xml file and PHY driver code in the Golden System
Reference Design (GSRD).
Receive path setup/hold
Only setup and hold for RX_CLK to RX_CTL and RXD[3:0] are necessary to consider
for receive timings. For Cyclone V/Arria V SoC HPS Dedicated I/O no other
consideration on the PHY side or board trace delay is required.
GUIDELINE: Hardware developers should specify the required FPGA skew so
that software developers can add the skew to the device driver code.
The hps_common_board_info.xml file is used to compile the Linux device tree for
the Cyclone V or Arria V SoC GSRD.
4.5.1.2. PHY Interfaces Connected Through FPGA I/O
Using FPGA I/O for an HPS EMAC PHY interface can be helpful when there is not
enough HPS Dedicated I/O left to accommodate the PHY interface or when you want
to adapt to a PHY interface not natively supported by the HPS EMAC.
GUIDELINE: Specify the PHY interface transmit clock frequency when
configuring the HPS component within Platform Designer (Standard).
For either GMII or MII, including adapting to other PHY interfaces, specify the
maximum transmit path clock frequency for the HPS EMAC PHY interface: 125 MHz for
GMII, 25 MHz for MII. This configuration results in the proper clock timing constraints
being applied to the PHY interface transmit clock upon Platform Designer (Standard)
system generation.
Related Information
• Embedded Peripherals IP User Guide
• Cyclone V RGMII Example Design
4.5.1.2.1. GMII/MII
MII and GMII are only available in Cyclone V/Arria V SoC by driving the EMAC signals
into the FPGA core routing logic and then ultimately to FPGA I/O pins or to internal
registers in the FPGA core.
GUIDELINE: Apply timing constraints and verify timing with Timing Analyzer.
Because routing delays can vary widely in the FPGA core and I/O structures, it is
important to read the timing reports, and especially for GMII, create timing
constraints. GMII has a 125 MHz clock and is single data rate unlike RGMII. GMII does
not have the same considerations for CLK-to-DATA skew though; its signals are
automatically centered by design by being launched with the negative edge and
captured with the rising edge.
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
39
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