Intel Cyclone V User Manual

Alternatively, consider routing the SPI master peripheral to FPGA, and using GPIO to
control the slave select signal.
Note: If you use this method, refer to the following Knowledge Base articles:
• Why does connecting HPS peripheral clocks to external pins via FPGA logic cause
Quartus fitter errors?
• Why does the HPS SPI Master fail when slave select is mapped to GPIO?
Related Information
• ctrlr0
For details about the ctrlr0.scph and ctrlr0.scpol bits in the Cyclone V
HPS, refer to "ctrlr0" in the "SPI Master" chapter of the Cyclone V Hard
Processor System Technical Reference Manual.
• ctrlr0
For details about the ctrlr0.scph and ctrlr0.scpol bits in the Arria V
HPS, refer to "ctrlr0" in the "SPI Master" chapter of the Arria V Hard Processor
System Technical Reference Manual.
4. Board Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
48

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524