Intel Cyclone V User Manual

Enabling HPS-to-FPGA Bridges from the Preloader
The Preloader checks the status of the FPGA and automatically enables bridges
configured in Platform Designer (Standard) and the BSP if the FPGA is configured. The
Preloader supports programming the FPGA before running automatic bridge enable
tests and code.
For more information, refer to GSRD v13.1 - Programming FPGA from HPS.
Enabling HPS-to-FPGA Bridges from U-Boot
The bridge_enable_handoff command can be run from the U-boot command
prompt to enable bridges. This command puts the HPS and SDRAM into a safe state
before enabling all bridges after appropriate checks.
For more information, refer to the KDB solution: How can I enable the FPGA2SDRAM
bridge on Cyclone V SoC and Arria V SoC Devices?
5. Embedded Software Design Guidelines for SoC FPGAs
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
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Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524