Intel Cyclone V User Manual

Document Version Description
• "Board Design Guidelines for SoC FPGAs" chapter:
— RGMII supported by HPS dedicated I/O
— Guidelines added:
• If your design uses QSPI flash with 4-byte addressing, design the
board to ensure that the QSPI flash is reset or power-cycled whenever
the HPS is reset.
• If your SPI peripheral requires the SPI master slave select to stay low
during the entire transaction period, consider using GPIO as slave
select, or configure the SPI master to assert slave select during the
transaction.
• Ensure that the SD/MMC card is reset whenever the HPS is reset.
• For bare-metal applications, avoid using a QSPI flash device larger
than 16 MB
• With a QSPI device larger than 16 MB, use QSPI extended 4-byte
addressing commands if supported by the device
• "Embedded Software Design Guidelines for SoC FPGAs" chapter:
— Reference DTB for NAND-based boot no longer supplied
— Clarify NAND flash interface type required for booting support
2017.02.20 Initial Release
B. Additional Information
AN-796 | 2018.06.18
AN 796: Cyclone V and Arria V SoC Device Design Guidelines
72

Intel Cyclone V Specifications

General

FPGA Family	Cyclone V
Logic Elements	25K to 301K
Transceivers	Up to 12
Processor	Dual-core ARM Cortex-A9
Process Technology	28 nm
Embedded Memory	M10K blocks
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -40°C to +125°C (Automotive)
Power Consumption	Varies by configuration and usage
Maximum User I/O	Up to 524