Intel Desktop Board DN2800MT Technical Product Specification
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Table 53. Port 80h POST Codes
Port 80 Code Progress Code Enumeration
ACPI S States
0x00,0x01,0x02,0x03,0x04,0x05 Entering S0, S2, S3, S4, or S5 state
0x10,0x20,0x30 Resuming from S2, S3, S4, or S5 state
PEI Platform driver
0x11 Set boot mode, GPIO init
0x12 Early chipset register programming
0x13 Basic chipset init
0x14 LAN init
0x15 Exit early platform init driver
PEI SMBUS
0x16 SMBUS driver init
0x17 Entry to SMBUS execute read/write
0x18 Exit SMBUS execute read/write
Memory
0x21 MRC entry point
0x24 Detecting presence of memory DIMMs
0x25 Override Detected DIMM settings
0x27 Configuring memory
0x28 Testing memory
PEIMs/Recovery
0x31 Crisis Recovery has initiated
0x33 Loading recovery capsule
0x34 Start recovery capsule / valid capsule is found
CPU PEI Phase
0x41 Begin CPU PEI Init
0x42 XMM instruction enabling
0x43 End CPU PEI Init
CPU PEI SMM Phase
0x44 Begin CPU SMM Init smm relocate bases
0x45 Smm relocate bases for APs
0x46 End CPU SMM Init
CPU DXE Phase
0x47 CPU DXE Phase begin
0x48 Refresh memory space attributes according to MTRRs
0x49 Load the microcode if needed
0x4A Initialize strings to HII database
0x4B Initialize MP support
0x4C CPU DXE Phase End
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