646265-004 17
Intel
®
Ethernet Network Adapter E810-XXVDA4T
User Guide
In the following example, the ens260f0 net interface exposes pins through the ptp7 interface:
#ls -R /sys/class/net/*/device/ptp/*/pins
/sys/class/net/ens260f0/device/ptp/ptp7/pins:
GNSS SMA1 SMA2 U.FL1 U.FL2
Users can also run ethtool -T <interface_name> to show the PTP clock number.
# ethtool -T <interface_name>
PTP Hardware Clock: 7
The E810 only has one hardware timer shared between all ports. As a result, users find the PTP clock
number only on Port 0.
If users need to use bonding or DPDK, do not use Port 0, as this prevents the use of Linux PHC API for
the device. A better solution is to use any other port for this functionality or to use a virtual function for
DPDK.
4.2 DPLL Priority
The E810-XXVDA4T automatically switches reference inputs according to the default DPLL priority list,
as shown in Table 6.
where:
Note: The DPLL priority list can be changed. See Section 4.11, “Advanced DPLL Configuration”.
Pin index = DPLL device physical pin index
EEC - DPLL0 = Ethernet equipment clock source from DPLL0 for frequency adjustments.,
glitchless.
PPS - DPLL1 = 1PPS generation from DPLL1 for phase adjustments. Glitches allowed. Slower
locking.
Table 6. DPLL Priority List
Default
Priority
Pin
Index
EEC - DPLL0
(Frequency/Glitchless)
Frequency
PPS - DPLL1 (Phase/Glitch
Allowed)
Frequency
0 6 1PPS from GNSS (GNSS-1PPS) 1PPS 1PPS from GNSS (GNSS-1PPS) 1PPS
1 4 1PPS from SMA1 (SMA1) 1PPS 1PPS from SMA1 (SMA1) 1PPS
2 5 1PPS from SMA2 (SMA2) 1PPS 1PPS from SMA2 (SMA2) 1PPS
3 1 Reserved --- 1PPS from CVL (CVL-SDP20) 1PPS
4 2 Recovered CLK1 (C827_0-RCLKA) 1.953125 MHz Recovered CLK1 (C827_0-RCLKA) 1.953125 MHz
5 3 Recovered CLK2 (C827_0-RCLKB) 1.953125 MHz Recovered CLK2 (C827_0-RCLKB) 1.953125 MHz
6 - Reserved --- Reserved ---
7 - Reserved --- Reserved ---
8 0 1PPS from CVL (CVL-SDP22) 1PPS 1PPS from CVL (CVL-SDP22) 1PPS
9 - OCXO 20.000 MHz OCXO 20.000 MHz
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