Intel
®
Ethernet Network Adapter E810-XXVDA4T
User Guide
24 646265-004
DPLL monitoring can be enabled (on) or disabled (off) by using the ethtool command in the Linux
kernel.
# export ETH=ens801f0
ethtool --show-priv-flags $ETH
Private flags for ens801f0:
link-down-on-close : off
fw-lldp-agent : off
channel-inline-flow-director : off
channel-inline-fd-mark : off
channel-pkt-inspect-optimize : on
channel-pkt-clean-bp-stop : off
channel-pkt-clean-bp-stop-cfg: off
vf-true-promisc-support : off
mdd-auto-reset-vf : off
vf-vlan-prune-disable : off
legacy-rx : off
dpll_monitor : on
extts_filter : off
Enabling DPLL monitoring:
ethtool --set-priv-flags $ETH dpll_monitor on
Disabling DPLL monitoring:
ethtool --set-priv-flags $ETH dpll_monitor off
4.11 Advanced DPLL Configuration
4.11.1 pin_cfg User Readable Format
The DPLL on the E810-XXVDA4T offer some advanced configuration options. These options are not
needed on regular applications and can cause problems. Please use these commands with extra care.
The DPLL will go back to the default values after a power cycle of the adapter.
The E810-XXVDA4T supports embedded sync (eSync), including embedded pulse per second (ePPS),
but not embedded pulse per two seconds (ePP2S).
Timing signals on the SMAs can be configured as inputs or outputs, typically configured for one pulse
per second (1PPS) operation, but they will support a 10 MHz signal (with or without the embedded 1PPS
eSync).
Note: Do not change any other output pin than 0 and 1.
To check the DPLL pin configuration:
# cat /sys/class/net/ens4f0/device/pin_cfg
in
| pin| enabled| state| freq| phase_delay| eSync| DPLL0 prio| DPLL1 prio|
| 0| 1| invalid| 1| 0| 0| 8| 8|
| 1| 1| invalid| 1| 0| 0| 15| 3|
| 2| 1| invalid| 1953125| 0| 0| 4| 4|
| 3| 1| invalid| 1953125| 0| 0| 5| 5|
Did this document help answer your questions?
To Next Page
Loading...
Need help?
General