Intel E810 VDA4T Series User Manual

Intel
®
Ethernet Network Adapter E810-XXVDA4T
User Guide
26 646265-004
Example:
# export ETH=enp1s0f0
Set freq to 10 MHz on input pin 4: DPLL will lock only if 10 MHz signals arrive on SMA1 and it has
been enabled for input.
# echo "in pin 4 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg
Set freq to 10 MHz on output pin 1: SMA2 will drive 10 MHz signal with embedded 1PPS if it has
been enabled for output.
# echo "out pin 1 freq 10000000 eSync 1" > /sys/class/net/$ETH/device/pin_cfg
Disable input pin 2: DPLL will ignore anything on pin 2.
# echo "in pin 2 enable 0" > /sys/class/net/$ETH/device/pin_cfg
Set freq to 1 Hz (1PPS) on input pin 4: DPLL will lock only if 1 Hz signals arrive on SMA1 and it has
been enabled for input with phase delay of 4 ns.
# echo "in pin 4 freq 1 phase_delay 4" > /sys/class/net/$ETH/device/pin_cfg
4.11.2 dpll_<X>_ref_pin/dpll_<X>_state Machine Readable Interface
(X = 0 /1)
# export ETH=enp1s0f0
To find out which pin the DPLL0 (EEC DPLL) is locked on, check the dpll_0_ref_pin:
# cat /sys/class/net/$ETH/device/dpll_0_ref_pin
To check the state of the DPLL0 (EEC DPLL), check the dpll_0_state:
# cat /sys/class/net/$ETH/device/dpll_0_state
DPLL_UNKNOWN = -1,
DPLL_INVALID = 0,
DPLL_FREERUN = 1,
DPLL_LOCKED = 2,
DPLL_LOCKED_HO_ACQ = 3,
DPLL_HOLDOVER = 4
To find out which pin the DPLL1 (PPS DPLL) is locked on, check the dpll_1_ref_pin:
# cat /sys/class/net/$ETH/device/dpll_1_ref_pin
To check the state of the DPLL1 (PPS DPLL), check the dpll_1_state:
# cat /sys/class/net/$ETH/device/dpll_1_state
The dpll_0_state interface used by synce4l as well.
Note: The user application can monitor the dpll_<X>_state and dpll_<X>_ref_pin to detect the
DPLL status changes. These changes will be visible in the dmesg as well.
Note: The application can also check the DPLL name in the dpll_<X>_name file.
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Intel E810 VDA4T Series Specifications

General

Product Series	E810
Product Type	Network Adapter
Interface Type	PCI Express 4.0 x16
Number of Ports	4
Data Link Protocol	10 Gigabit Ethernet
Ports	4 x 10GBASE-T
Virtualization	SR-IOV, VMDq
Operating Temperature	0°C to 55°C
Storage Temperature	-40°C to 70°C
Model	VDA4T
Data Rate	10 Gbps
Supported Protocols	Ethernet, iSCSI

Summary

Revision History

1.0 Introduction

1.1 Reference Documents

Lists related documents available on the Intel Resource and Design Center.

2.0 E810-XXVDA4T Ethernet Network Adapter

2.1 E810-XXVDA4T Features

Details the key features and capabilities of the E810-XXVDA4T adapter.

2.2 Architecture

Describes the block diagram and physical layout of the E810-XXVDA4T.

2.3 Synchronization Signaling

Explains the 1PPS and 10 MHz signaling using SMA and U.FL connectors.

2.4 Optional GNSS Module

Details the functionality and features of the optional GNSS module.

3.0 Software, Firmware, and Drivers

3.1 Software Support/Packages

Lists supported operating systems and required software for the E810 adapter.

3.2 Building a linuxptp Project

Instructions for downloading, compiling, and installing the linuxptp project.

3.3 Related linuxptp Information

Links to additional resources for the linuxptp project.

3.4 Building a synce4l Tool

Steps to download, compile, and install the synce4l tool.

4.0 Configuring the E810-XXVDA4T Using the Linux Kernel Interface

4.1 Introduction

Overview of the Linux kernel interface for controlling synchronization pins.

4.2 DPLL Priority

Explains the default DPLL priority list for reference input switching.

4.3 External Connectors

Details the SMA and U.FL connectors for timing signals.

4.4 Channel 1 Configurations

Configuration examples for SMA1 and U.FL1 for 1PPS input/output.

4.5 Channel 2 Configurations

Configuration examples for SMA2 and U.FL2 for 1PPS input/output.

4.6 Recovered Clocks (G.8261 SyncE Support)

How to enable and use recovered clocks for SyncE.

4.7 External Timestamp Signals

Using external 1PPS signals as time reference with ts2phc.

4.8 Periodic Outputs from DPLL (SMA and U.FL Pins)

Configuring periodic 1PPS outputs from DPLL.

4.9 Reading Status of the DPLL

Using debugfs to monitor the on-board DPLL device state.

4.10 DPLL Monitoring

Monitoring DPLL events and state changes via system log.

4.11 Advanced DPLL Configuration

Advanced configuration options for DPLL.

4.11.1 pin_cfg User Readable Format

Advanced configuration options for DPLL using pin_cfg.

4.11.2 dpll_<X>_ref_pin/dpll_<X>_state Machine Readable Interface (X = 0/1)

Machine readable interface for DPLL state and reference pin status.

4.12 1PPS Signals from E810 Device to DPLL

How E810 delivers 1PPS signals to DPLL for synchronization.

4.13 1PPS Signals from the DPLL to E810 Device

How DPLL delivers 1PPS signals to E810 for timestamping.

4.14 GNSS Module Interface

Interface for receiving NMEA messages from the optional GNSS module.

4.15 GNSS Advanced Features

Additional configuration for GNSS for best GM accuracy.

4.15.1 Prerequisites and Steps to Fully Enable GNSS Features

Prerequisites and installation steps for enabling GNSS features.

4.15.3 Perform Survey-In for New Location Setup

Process for achieving precise time information using GNSS survey-in.

4.15.4 Check Survey-In Status

Tracking survey-in status for successful GNSS synchronization.

4.15.5 Check GNSS Overall Configuration Performance

Checking antenna and GNSS receiver performance via TTFF.

5.0 Configuration Setup

5.1 Disable All SMA and U.FL Connections

Commands to disable all SMA and U.FL connectors.

5.2 PTP Grand Leader (GM) with Optional GNSS Module

Configuration for PTP Grand Leader using GNSS module.

5.3 PTP Grand Leader (GM) with External GNSS Clock

Configuration for PTP Grand Leader with an external GNSS clock.

5.4 Boundary Clock Configuration

Configuration for setting up the adapter as a Boundary Clock.

5.5 Port Configured as Follower

Configuration for setting up the adapter as a PTP Follower.

5.6 SyncE Setup

How to specifically set up Synchronous Ethernet (SyncE).

5.6.5 Two E810-XXVDA4T NICs Setup without GNSS and with 1PPS

Setup for two adapters without GNSS, with 1PPS connection.

5.6.6 Two E810-XXVDA4T with GNSS Connection Setup

Setup for two adapters with GNSS connection.

5.7 O-RAN Configuration 1

5.7.1 External Connections

External connections for O-RAN Configuration 1.

5.7.2 Software Configuration

Software configuration for O-RAN Configuration 1.

5.8 Example ts2phc Configuration File

Example ts2phc configuration file for BC.

5.9 Example ptp4l Configuration File for BC

Example ptp4l configuration file for Boundary Clock.

5.10 Example synce4l Configuration File for BC

Example synce4l configuration file for Boundary Clock.

6.0 Initial Test Setup

6.1 Test Diagram

Diagram illustrating the initial test setup with two adapters.

6.2 Software Configuration

Software configuration steps for the initial test setup.

6.2.1 Leader Adapter

Software configuration for the leader adapter in the test setup.

6.2.2 Follower Adapter

Software configuration for the follower adapter in the test setup.

6.2.3 Test Results

Displays and explains the results of the initial test setup.

Appendix A Notes

Appendix B Glossary and Acronyms