Intel E810 VDA4T Series User Manual

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Intel
®
Ethernet Network Adapter E810-XXVDA4T
User Guide
2.0 E810-XXVDA4T Ethernet Network Adapter
2.1 E810-XXVDA4T Features
Following are the features of the Intel
®
Ethernet Network Adapter E810-XXVDA4T:
• Based on Intel
®
Ethernet Controller E810 device using SFP28 form factor connections, as well as
inheriting most of the features from the Intel
®
Ethernet Network Adapter E810-XXVDA4 (E810-
XXVDA4).
• Software capability to configure the SMA signals via the standard Linux driver.
• Driver support for Linux PTP stack (ptp4l) to send synchronization messages and synchronize the
host system clock to the adapter's PHC. This is present in all Intel network adapters.
• Newly-developed utility (ts2phc) for the Linux PTP stack optimized for synchronizing the PHC to a
1PPS input, rather than PTP messages.
• When combined with an external GNSS 1PPS input, the features of the adapter and Linux PTP stack
provide the complete solution for a low cost PTP grand leader, while maintaining the ability to
provide the host system's LAN connectivity.
• Exposed PTP timing signals on a front panel using SMA connectors. This enables timing signals to
easily be connected by the end user after the adapter is installed in a system. Timing signals on the
SMAs can be configured as inputs or outputs, typically configured for one pulse per second (1PPS)
operation, but they will support a 10 MHz signal (with or without the embedded 1PPS eSync). The
rising edge of the 1PPS signal is used to mark the start of a new second, Top of Second (ToS). A
1PPS input signal is typically sourced from a GNSS module, or might be connected to the 1PPS
output of another adapter. Circuitry is provided on board for isolation, buffering, and level-shifting
to adapt the controller's CMOS signals for out-of-system use. Refer to Section 2.3 for 1PPS and
10 MHz signaling electrical requirements.
• In addition to the dual SMA connectors, the E810-XXVDA4T also includes two U.FL connectors for
1PPS and/or 10 MHz; one is output only and the other is input only. This enables hardware-level
traceability for connections to motherboards that do not have room for external SMA connectors.
• High accuracy reference clock. Intel adapters typically use on-board reference clocks with accuracy
in the range of ±50 parts per million (ppm) as required to meet the Ethernet PHY requirements.
Increased reference clock accuracy to ±2 parts per billion (ppb) can be achieved using an
Oven-Controlled Crystal Oscillator (OCXO). This tighter accuracy enables the PTP Hardware Clock
(PHC) inside the E810 to drift more slowly in the event the 1PPS source, or software adjustment via
1588 sync protocol, is lost. The ability to maintain time after the reference source is lost is known
as holdover. This is estimated to extend holdover time to ~4 hours for ±1.5 µs.
• Add support for Synchronous Ethernet (SyncE) clock recovery (ITU G.8262).
• Add a high-quality DPLL to support multiple input clock functions and multiple output frequencies.
The DPLL IC has separate integrated DPLL instances DPLL0 is used for generating high stability
clock signal and DPLL1 used for driving the output signals.
• The timing information from the DPLL (that can arrive from the GNSS module, SMA connectors,
E810 SDPs, or from the recovered SyncE signals) are routed to the E810 and can be used to
synchronize the PHC (PTP hardware clocks). All E810 ports share only one physical PHC, and this is
particularly useful in creating a Boundary Clock (BC) functionality like what is defined in ITU-T
G.8273.2 (but without SyncE).
• Add mounting and connection provision for an optional GNSS module on board. When installed, the
GNSS module provides the 1pps signal without the need for an external GNSS appliance. An I
2
C
interface provides a way to access the serial port data on the GNSS, including configuration options.
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Intel E810 VDA4T Series Specifications

General

Brand	Intel
Model	E810 VDA4T Series
Category	Adapter
Language	English