Intel Confidential 4
4.1.3.3 FLREG2—Flash Region 2 (Intel® ME) Register
(Flash Descriptor Records)..........................................................30
4.1.3.4 FLREG3—Flash Region 3 (GbE) Register
(Flash Descriptor Records)30
4.1.3.5 FLREG4—Flash Region 4 (Platform Data) Register
(Flash Descriptor Records)30
4.1.4 Flash Descriptor Master Section................................................................31
4.1.4.1 FLMSTR1—Flash Master 1 (Host CPU/ BIOS)
(Flash Descriptor Records)31
4.1.4.2 FLMSTR2—Flash Master 2 (Intel® ME)
(Flash Descriptor Records)31
4.1.4.3 FLMSTR3—Flash Master 3 (GbE)
(Flash Descriptor Records)31
4.1.5 PCH Softstraps.......................................................................................32
4.1.6 Descriptor Upper Map Section...................................................................32
4.1.6.1 FLUMAP1—Flash Upper Map 1
(Flash Descriptor Records)32
4.1.7 Intel
®
ME Vendor Specific Component Capabilities Table..............................32
4.1.7.1 JID0—JEDEC-ID 0 Register
(Flash Descriptor Records)..........................................................32
4.1.7.2 VSCC0—Vendor Specific Component Capabilities 0
(Flash Descriptor Records)32
4.1.7.3 JIDn—JEDEC-ID Register n
(Flash Descriptor Records)33
4.1.7.4 VSCCn—Vendor Specific Component Capabilities n
(Flash Descriptor Records)35
4.2 OEM Section .....................................................................................................36
4.3 Region Access Control ........................................................................................36
4.3.1 Intel Recommended Permissions for Region Access .....................................37
4.3.2 Overriding Region Access.........................................................................37
4.4 Intel
®
ME Vendor-Specific Component Capabilities (Intel
®
ME VSCC) Table...............38
4.4.1 How to Set a JEDEC ID Portion of Intel
®
ME VSCC Table Entry......................38
4.4.2 How to Set a VSCC Entry in
Intel
®
ME VSCC Table for Broadwell PCH-LP Platforms38
4.4.3 Intel
®
ME VSCC Table Settings for Broadwell PCH-LP Family Systems............40
5 Serial Flash Discoverable Parameter (SFDP) Overview..................................41
5.1 Introduction......................................................................................................41
5.2 Discoverable Parameter Opcode and Flash Cycle ....................................................41
5.3 Parameter Table Supported on PCH......................................................................42
5.4 Detail JEDEC Specification...................................................................................42
6 Configuring BIOS/GbE for SPI Flash Access ...................................................43
6.1 Unlocking SPI Flash Device Protection for Broadwell PCH-LP Platform........................43
6.2 Locking SPI Flash via Status Register ...................................................................44
6.3 SPI Protected Range Register Recommendations....................................................44
6.4 Software Sequencing Opcode Recommendations....................................................44
6.5 Recommendations for Flash Configuration
Lockdown and Vendor Component Lock Bits45
6.5.1 Flash Configuration Lockdown ..................................................................45
6.5.2 Vendor Component Lock..........................................................................45
6.6 Host Vendor Specific Component Control
Registers (VSCC)45
6.7 Host VSCC Register Settings ...............................................................................50
7 Flash Image Tool..................................................................................................51
7.1 Flash Image Details ...........................................................................................51
7.1.1 Flash Space Allocation.............................................................................52
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