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Intel Confidential
Serial Flash Discoverable Parameter (SFDP) Overview
5 Serial Flash Discoverable
Parameter (SFDP) Overview
5.1 Introduction
As the feature set of serial flash progresses, there is an increasing amount of
divergence as individual vendors find different solution to adding new functionality such
as speed and addressing.
These guidelines are a standard that will allow for individual vendors to have their value
add features, but will allow for a controller to discover the attributes needed to operate.
5.2 Discoverable Parameter Opcode and Flash Cycle
The discoverable parameter read opcode behaves like a fast read command. The
opcode is 5Ah and the address cycle is 24 bit long. After the opcode 5Ah is clocked in,
there are 24 bit of address clocked in. There will then be eight clock (8 wait states)
before valid data is clocked out. There is flexibility in the number of wait states, but
they must be byte aligned (multiple of 8 wait states).
SFDP read must update at a frequency between 17 MHz and 66 MHz with a single byte
of wait state.
Figure 5-1. SFDP Read Instruction Sequence
Wait States
24 Bit
Address
Dis covery
Opcode
0
1
23 76 5
4
32 1
0
765 43 21 0
6543210 7 8 9 10 28 29 3031
212322
32 33343536373839 4041424344454647
7
CS#
CLK
SI
SO
Data Byte
Data Byte
Addr + 1h
Hi gh Z
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