Intel PCH-LP - Broadwell PCH-LP SPI AC Electrical Compatibility Guidelines; SPI Timing; SPI Timings (20 Mhz); SPI Timings (33 Mhz)

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Intel Confidential
PCH SPI Flash Compatibility Requirement
3.2 Broadwell PCH-LP SPI AC Electrical Compatibility
Guidelines
Notes:
1.Typical clock frequency driven by Broadwell PCH-LP Family is 17.86 MHz.
2.Measurement point for low time and high time is taken at .5(VccME3_3).
Notes:
1.Typical clock frequency driven by Broadwell PCH-LP Family is 31.25 MHz.
2.Measurement point for low time and high time is taken at .5(VccME3_3).
Table 3-1. SPI Timings (20 MHz)
Sym Parameter Min Max Units Notes
t180a Serial Clock Frequency - 20MHz Operation 17.06 18.73 MHz 1
t183a
Tco of SPI_MOSI with respect to serial clock falling
edge at the host
-5 13 ns
t184a
Setup of SPI_MISO with respect to serial clock falling
edge at the host
16 - ns
t185a
Hold of SPI_MISO with respect to serial clock falling
edge at the host
0-ns
t186a
Setup of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host
30 - ns
t187a
Hold of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host
30 - ns
t188a SPI_CLK High time 26.37 - ns 2
t189a SPI_CLK Low time 26.82 - ns 2
Table 3-2. SPI Timings (33 MHz)
Sym Parameter Min Max Units Notes
t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.81 MHz 1
t183b
Tco of SPI_MOSI with respect to serial clock falling
edge at the host
-5 5 ns
t184b
Setup of SPI_MISO with respect to serial clock falling
edge at the host
8-ns
t185b
Hold of SPI_MISO with respect to serial clock falling
edge at the host
0-ns
t186b
Setup of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host
30 - ns
t187b
Hold of SPI_CS[1:0]# assertion with respect to serial
clock rising edge at the host
30 - ns
t188b SPI_CLK High time 14.88 - ns 2
t189b SPI_CLK Low time 15.18 - ns 2