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Intel Confidential
APPENDIX A - Descriptor Configuration
A.17 PCHSTRP15—Strap 15 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 03Ch Size: 32 bits
Default Flash Address: 13Ch
Recommended Value:
Bits Description Usage
31:25 Reserved, set to ’0’
24 PCIe* Power Stable Timer (t205b timer)
0 = t205b timer is disabled (default)
1 = PCH will count 99ms from PWROK assertion before
PLTRST# is de-asserted.
Board dependent.
Default is disabled, Platform is required to ensure
timing of PWROK and SYS_PWROK in such a way that
it satisfies the PCIe timing requirement of power
stable to reset de-assertion.
23:21 Reserved, set to ’0’
20 DeepSx Platform Configuration
(DEEPSX_PLT_CFG_SS)
0 = The platform does not support DeepSx.
1 = The platform supports DeepSx
19 LAN PHY Power Up Time (LAN_PHY_PU_TIME)
0 = 100ms
1 = 50ms (default)
This bit determines how long the delay for LAN PHY to
power up after de-assertion of SLP_LAN#.
18:16 Reserved, set to ’0’
15 SLP_WLAN# or GPIO29/MGPIO3 Select
(SLP_WLAN#_GP29MGPIO3_SEL)
0 = SLP_WLAN#
1 = GPIO29/MGPIO3
14 SMLink1 Thermal Reporting Select
(SMLINK1_THERM_SEL)
0 = Reserved.
1 = PCH temperature (1 byte of data) will be available for
polling out on SMLink1. Processor and DIMMs
temperature monitoring will require an external device.
Always set this bit to 1b.
13:12 Reserved, set to ’0’
11:10 t210 Timing
00: 1 ms (default)
01: 30 us
10: 5 ms
11: 2 ms
t210: PROCPWRGD and SYS_PWROK high to
SUS_STAT# deassertion. Refer to EDS for details.
9:8 t209 Timing
00: 100 ms
01: 50 ms
10: 5 ms
11: 1 ms (default)
t209: PCH clock output stable to PROCPWRGD high.
Refer to EDS for details.
7 Reserved, set to ’0’
6 Intel integrated wired LAN Enable (IWL_EN)
0 = Disable Intel integrated wired LAN Solution
1 = Enable Intel integrated wired LAN Solution
Notes: This must be set to '1' if the platform is using Intel's
integrated wired LAN solution. Set to ’0’ if not using
Intel integrated wired LAN solution or if disabling it.
This must be set to '1' if the platform is using Intel's
integrated wired LAN solution.
This must be set to ’0’ if not using Intel’s integrated
wired LAN solution or if disabling it.
5:0 Chipset configuration, set to’111110b’
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