523462 81
Intel Confidential
APPENDIX A - Descriptor Configuration
A.11 PCHSTRP9—Strap 9 Record (Flash Descriptor
Records)
Flash Address: FPSBA + 024h Size: 32 bits
Default Flash Address: 124h
Bits Description Usage
31:30
Reserved, set to ’0’.
29:28
Chipset configuration. set to’11’b
27:23
Reserved, set to ’0’.
22
TEMP_ALERT# or SML1ALERT# Select
(TEMP_ALERT#_SML1ALERT#_SEL)
This strap determines the native mode operation of GPIO73
0 = SML1ALERT# is the native functionality of GPIO73
1 = TEMP_ALERT# is the native functionality of GPIO73
TEMP_ALERT# is used to indicate the PCH
temperature out of bounds condition to an external
agent EC, when PCH temperature is greater than
value programmed by BIOS.
21:20 USB3 Port 4 PCIe* Port 2 Mode
(USB3P4_PCIEP2_MODE)
00 : PCIe Lane 2 is statically assigned to PCI Express (or
GbE)
01 : PCIe Lane 2 is statically assigned to USB3 Port 4
10 : Reserved.
11 : Reserved.
This soft strap sets the default value of the USB3 PCI
Express* Port2 Mode register that resides in the core
well.
Note: Autodetect of USB3/PCIe and ExpressCard
are not supported
19:18 USB3 Port 3 PCIe Port 1 Mode
(USB3P3_PCIEP1_MODE)
00 : PCIe Lane 1 is statically assigned to PCI Express (or
GbE)
01 : PCIe Lane 1 is statically assigned to USB3 Port 3
10 : Reserved.
11 : Reserved.
This soft strap sets the default value of the USB3 PCI
Express Port1 Mode register that resides in the core
well.
Note: Autodetect of USB3/PCIe and ExpressCard
are not supported
17:15 Reserved, set to ‘0’
14 Subtractive Decode Agent Enable (SUB_DECODE_EN):
0 = Disable PCIe ports from Subtractive Decode Agent
1 = Enable PCIe ports to behave as a subtractive decode
agent
Note: If connecting to PCI bridge chip to PCH that requires
PCH to behave as a subtractive decode agent, then
set this bit to 1b.
Note: This setting is not the same for all designs,
dependent on the board implementation.
This field must be determined by platform
hardware engineer.
13:12 Reserved, set to ‘0’
11
Intel PHY Over PCI Express Enable (PHY_PCIE_EN):
0 = Intel integrated wired MAC/PHY communication is not
enabled over PCI Express*.
1 = The PCI Express* port selected by the
PHY_PCIEPORT_SEL soft strap to be used by Intel
PHY
Note: This bit must be “1” if using Intel integrated wired
LAN solution.
This bit MUST be set to ’1’ if using Intel integrated
wired LAN solution.
If not using, or if disabling Intel integrated wired LAN
solution then set this to ’0’.
To Next Page
Loading...
Need help?
General
