Intel S1200BTS User Manual

Glossary Intel® Server Board S1200BT TPS
Revision 1.0
Intel order number G13326-003
138
Term
Definition
Hz
Hertz (1 cycle/second)
I2C
Inter-Integrated Circuit Bus
IA
Intel
®
Architecture
IBF
Input Buffer
ICH
I/O Controller Hub
ICMB
Intelligent Chassis Management Bus
IERR
Internal Error
IFB
I/O and Firmware Bridge
ILM
Independent Loading Mechanism
IMC
Integrated Memory Controller
INTR
Interrupt
I/OAT
I/O Acceleration Technology
IOH
I/O Hub
IP
Internet Protocol
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
IR
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
Keyboard Controller Style
KVM
Keyboard, Video, Mouse
LAN
Local Area Network
LCD
Liquid Crystal Display
LDAP
Local Directory Authentication Protocol
LED
Light Emitting Diode
LPC
Low Pin Count
LUN
Logical Unit Number
MAC
Media Access Control
MB
1024 KB
MCH
Memory Controller Hub
MD2
Message Digest 2 – Hashing Algorithm
MD5
Message Digest 5 – Hashing Algorithm – Higher Security
ME
Management Engine
MMU
Memory Management Unit
ms
Milliseconds
MTTR
Memory Type Range Register
Mux
Multiplexor
NIC
Network Interface Controller
NMI
Non-maskable Interrupt
OBF
Output Buffer
OEM
Original Equipment Manufacturer
Ohm
Unit of electrical resistance
OVP
Over-voltage Protection

Intel S1200BTS Specifications

General

Chipset	Intel C204 Chipset
Form Factor	MicroATX
Processor Socket	LGA 1155
Number of Processors Supported	1
Number of Memory Slots	4
Processor Support	Intel Xeon E3-1200 series
Memory Support	DDR3 ECC UDIMM
Expansion Slots	1 PCI-E x16 Gen3, 1 PCI-E x4 Gen2, 1 PCI-E x1 Gen2, 1 PCI 32bit/33MHz
Storage	4 x SATA 3Gb/s, 2 x SATA 6Gb/s
Network Interface	Dual Gigabit Ethernet ports
Memory Speed	1333 MHz
RAID Supported	RAID 0, 1, 5, 10
USB Ports	4 rear