Intel S1200BTS User Manual

Intel® Server Board S1200BT TPS BIOS User Interface
Revision 1.0
Intel order number G13326-003
47
6. BIOS User Interface
6.1 BIOS POST Initialization
6.1.1 BIOS Revision Identification
6.1.1.1 BIOS ID String
The BIOS Identification string is used to uniquely identify the revision of the BIOS being used
on the server. The BIOS ID string is displayed on the Power On Self Test (POST) diagnostic
screen and in Setup and System Management BIOS (SMBIOS) structures.
The BIOS ID string is formatted as follows:
6.1.1.2 BoardFamilyID.OEMID.MajorVer.RelRev.RelNum.BuildDateTime
Where:
 BoardFamilyID = String name for to identify board family.
- ―S1200BT‖ is used to identify BIOS builds for S1200BT server boards.
 OEMID = Three-character OEM BIOS Identifier, to identify the board BIOS ―owner‖.
Changed only if and when BIOS Development management authorizes a BIOS program
for a specific OEM customer.
- ―86B‖ is used for BIOS Releases.
 MajorVer = Major Version, two decimal digits 01-99 which are changed only to identify
major hardware or functionality changes that affect BIOS compatibility between boards.
- ―01‖ is the starting BIOS Major Version for all platforms. This designation can change
only at the discretion of BIOS Development management.
 RelRev = Release Revision, two decimal digits 00-99 which are changed to identify
specific "point releases" or branches based on a given BIOS Release but with targeted
minor fixes or special-purpose differences in functionality from the primary BIOS
Release. The Release Revision first digit is incremented for each initial revision of a
BIOS Release. The second digit will increment only if a revision itself needs to be
revised with a change or fix. The Release Number will not change when a BIOS is built
as a Release Revision and will reset to ―00‖ with each new Release Number.
- ―00‖ is the starting Release Revision for all platform BIOS Releases. Release Revisions
are not Standard Operating Procedure, but may be produced if authorized BIOS
management.
The sequence will be as in the following examples for Release Revision and Release Number:
 Release 2 (i.e., 2.0) = RelRev/RelNum ―.00.0002‖
 Release 2 Revision 1(i.e., 2.1) = RelRev/RelNum ―.10.0002‖
 Release 2 Revision 1 fix 1 (i.e., 2.11) = RelRev/RelNum ―.11.0002‖
 Release 3 (i.e., 3.0) = reverts to RelRev/RelNum ―.00.0003‖

Intel S1200BTS Specifications

General

Chipset	Intel C204 Chipset
Form Factor	MicroATX
Processor Socket	LGA 1155
Number of Processors Supported	1
Number of Memory Slots	4
Processor Support	Intel Xeon E3-1200 series
Memory Support	DDR3 ECC UDIMM
Expansion Slots	1 PCI-E x16 Gen3, 1 PCI-E x4 Gen2, 1 PCI-E x1 Gen2, 1 PCI 32bit/33MHz
Storage	4 x SATA 3Gb/s, 2 x SATA 6Gb/s
Network Interface	Dual Gigabit Ethernet ports
Memory Speed	1333 MHz
RAID Supported	RAID 0, 1, 5, 10
USB Ports	4 rear