Intel S1200BTS User Manual

Intel® Server Board S1200BT TPS Functional Architecture
Revision 1.0
Intel order number G13326-003
25
 JTAG Master
 Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are
SMBus 2.0 compliant.
 Parallel general-purpose I/O Ports (16 direct, 32 shared)
 Serial general-purpose I/O Ports (80 in and 80 out)
 Three UARTs
 Platform Environmental Control Interface (PECI)
 Six general-purpose timers
 Interrupt controller
 Multiple SPI flash interfaces
 NAND/Memory interface
 Sixteen mailbox registers for communication between the Integrated BMC and host
 LPC ROM interface
 Integrated BMC watchdog timer capability
 SD/MMC card controller with DMA support
 LED support with programmable blink rate controls on GPIOs
 Port 80h snooping capability
 Secondary Service Processor (SSP), which provides the HW capability of offloading
time critical processing tasks from the main ARM core.

Intel S1200BTS Specifications

General

Chipset	Intel C204 Chipset
Form Factor	MicroATX
Processor Socket	LGA 1155
Number of Processors Supported	1
Number of Memory Slots	4
Processor Support	Intel Xeon E3-1200 series
Memory Support	DDR3 ECC UDIMM
Expansion Slots	1 PCI-E x16 Gen3, 1 PCI-E x4 Gen2, 1 PCI-E x1 Gen2, 1 PCI 32bit/33MHz
Storage	4 x SATA 3Gb/s, 2 x SATA 6Gb/s
Network Interface	Dual Gigabit Ethernet ports
Memory Speed	1333 MHz
RAID Supported	RAID 0, 1, 5, 10
USB Ports	4 rear