Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture
Revision 1.3
17
Table 3. Processor Support Matrix
Process Name Socket
Core
Frequency
Cache size FSB Frequency
Dual-Core Intel
®
Xeon
®
processor 3000 series
Intel
®
LGA775
1.86GHz –
2.66GHz
2MB or 4MB 1066MHz
Quad -Core Intel
®
Xeon
®
processor 3200 series
Intel
®
LGA775
2.13GHz –
2.40GHz
8MB 1066MHz
Dual-Core Intel
®
Xeon
®
processor 3100 series
Intel
®
LGA775 TBD TBD 1333MHZ
Dual-Core Intel
®
Xeon
®
processor 3300 series
Intel
®
LGA775 TBD TBD 1333MHZ
3.2 Intel
®
3200/3210 Chipset
The server board is designed around the Intel
®
3200/3210 Chipset. The chipset provides an
integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI Express*).
The chipset consists of three primary components.
3.2.1
Intel
®
3200/3210 Chipset MCH: Memory Control Hub
The Intel
®
3200/3210 Chipset is designed for use with Intel
®
processors in a UP server platform.
The role of the MCH in the system is to manage the flow of information between its four
interfaces:
• Processor Interface (FSB)
• System Memory Interface (DDR2)
• DMI interface to ICH9R South Bridge
• PCI Express* connectivity to one or two PCIe* x8 connectors
The feature list of the MCH includes:
• Processor / Host Interface
− Supports LGA775 processors in a UP System configuration
− 200/266/333 MHz FSB Clock frequency
− GTL+ bus drivers with integrated GTL termination resistors
• System Memory Controller
− Supports 512Mbit and 1Gbit memory technologies
− DDR2 – 667, 800 MHz
− 8GB addressable memory
− Supports unbuffered, ECC and non-ECC DIMMs
− No support for DIMMs less than 512MB and memory speeds less than 667MHz
• DMI Interface
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