Intel S3210SHLX - Entry Server Board Motherboard - Interrupt Routing; Table 15. PCI and PCI-X* Interrupt Routing;Sharing

Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
Revision 1.3
32
3.4.1.2 PCI Interface for Video subsystem
The server board graphics subsystem is connected to the Intel
®
ICH9R via a PCIe* x1 bus.
3.4.2 Interrupt Routing
The board interrupt architecture accommodates both PC-compatible PIC mode and APIC mode
interrupts through use of the integrated I/O APICs in the Intel
®
ICH9R.
3.4.2.1 Legacy Interrupt Routing
For PC-compatible mode, the Intel
®
ICH9R provides two 82C59-compatible interrupt controllers.
The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary
interrupt controller (standard PC configuration). A single interrupt signal is presented to the
processor, to which the processor will respond for servicing. The Intel
®
ICH9R contains
configuration registers that define which interrupt source logically maps to I/O APIC INTx pins.
The Intel
®
ICH9R handles both PCI and IRQ interrupts. The Intel
®
ICH9R translates these to the
APIC bus. The numbers in the table below indicate the Intel
®
ICH9R PCI interrupt input pin to
which the associated device interrupt (INTA, INTB, INTC, INTD, INTE, INTF, INTG, INTH for
PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is connected. The Intel
®
ICH9R I/O APIC exists on the I/O APIC bus with the processor.
Table 15. PCI AND PCI-X* Interrupt Routing/Sharing
Interrupt INT A INT B INT C INT D
Intel
®
82541PI LAN (NIC2) PIRQB
Integrated BMC PIRQC
PCI Slot 1 (PCI 32bit/33MHz) PIRQG PIRQF PIRQE PIRQH
PCI Slot 2 (PCI 32bit/33MHz) PIRQF PIRQG PIRQH PIRQE
PCI-X* Slot 5 (64bit/133MHz) (LX board SKU
only)
PXIRQ5 PXIRQ6 PXIRQ7 PXIRQ4
PCI-X* Slot 6 (64bit/133MHz) (Riser, LX board
SKU only)
PXIRQ0 PXIRQ1 PXIRQ2 PXIRQ3
3.4.2.2 APIC Interrupt Routing
For APIC mode, the server board interrupt architecture incorporates three Intel
®
I/O APIC
devices to manage and broadcast interrupts to local APICs in each processor. The Intel
®
I/O
APICs monitor each interrupt on each PCI device; including PCI slots in addition to the ISA
compatibility interrupts IRQ (0-15).
When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.