Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
Revision 1.3
38
• Unique Chip ID for each part, burned at the time production testing
• Hardware 32-bit Random Number generator
• JTAG Master interface
• On-Chip Test Infrastructure for testing BMC firmware
Graphics Controller Subsystem
• Integrated Matrix Graphics Core
• 2D Hardware Graphics Acceleration
• DDR-2 memory interface supports up to 128Mbytes of memory
• Supports all display resolutions up to 1600 x 1200 16bpp @ 75Hz
• High speed Integrated 24-bit RAMDAC
• Single lane PCI Express* host interface
ARM926EJ-S
16K D & I
Cache
Interrupt
Controller
Fan Tach (12)
PWM (4)
ADC
Thermal
USB 1.1
&
USB 2.0
LPC Master,
JTAG Master,
& SPI FLash
UART (3) GPIO
KCS
BT &
Mailboxes
System
Wakeup
Control
LPC
Interface
Graphics
Controller
BMC & KVMS Subsystem
BMC & KVMS Subsystem Graphics Subsystem
RTC &
General Purpose
TImers (3)
UART
(3)
I2C
(6)
Ethernet
MAC with
RMII (2)
Crypto
Accelerator
DDR-II
16-bit
Memory
Controller
LPC to SPI
Flash Bridge
Watchdog
Timer
Real Time Clock
Interface
(external RTC)
LPC
Interface
To Host
Video
Output
PCIe x1
Interface
DDR-II
(up to
667MHz)
JTAG
Master
Code
Memory
USB
to Host
Integrated BMC Block Diagram
3.6 PCIe* to PCI-X* Bridge 6702PXH (PXH-V) (LX Board SKU Only)
The Intel 6702PXH 64-bit PCI Hub is a peripheral chip that performs PCI bridging
functions between the PCI Express* interface and the PCI bus. The Intel 6702PXH 64-bit
PCI Hub contains a single PCI bus interface that can be configured to operate in PCI (33
or 66 MHz) or PCI-X* Mode 1 (66, 100, or 133 MHz).