Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture
Revision 1.3
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The SPI flash meets the following requirements:
• Erase size capability of 4 Kbyte or 64 Kbyte
• SPI device meets the command set per Table 9.
Command and opcode C7h for Full Chip Erase is recommended for streamlined software
development.
• Supports JEDEC ID OP Code 9FH
• Support multiple writes to a page without requiring a preceding command (minimum 512
writes)
• Ignores the upper address bit such that an address of FFFFFFFFh simply aliases to the
top of the flash memory.
• SPI Compatibility Mode 0
• Receipt of an unsupported command causes a completed cycle without impact to the
flash content
• Minimum density of 16 Mb (BIOS + Gbe)
• Power up in an unlocked state or use the write status register to disable write protection.
Table 9: SPI Required Command Codes
Commands Opcode Notes
Write Status 01h
If Command is supported, 01h must be the
opcode.
Program Data 02h WRITE DATA / PROGRAM DATA
Read Data 03h
Write Disable 04h
Read Status 05h
Write Enable 06h
If command is supported, 06h must be the
opcode
Fast Read 0Bh
Enable Write
Status Register
50 or 06h
Erase Programmable 256B, 4kbyte, 8 Kbyte or 64 Kbyte erase
JEDEC ID 9Fh
JEDEC Standard Manufacturer and Device
ID read method is defined in Standard
JESD21-C, PRN03-NV1.
The SPI Flash Memory device is the Atmel* AT26DF321 a 32-megabit, 2.7 to 3.6 volt serial
interface FLASH memory, Intel part number D64145-001/D64145-002. The AT26DF321
supports the block erase command opcodes 20H and D8H providing respectively 4-Kbytes or
64-Kbytes block erase sizes. This is installed directly onto the server board without the use of
sockets.
3.2.3.15 Manageability
The ICH9 integrates several functions designed to manage the system and lower the total cost
of ownership (TCO) of the system. These system management functions are designed to report
errors, diagnose the system, and recover from system lockups without the aid of an external
microcontroller.
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