Intel S3210SHLX - Entry Server Board Motherboard - Table 16. Interrupt Definitions

Intel® Server Boards S3200SH/S3210SH TPS Functional Architecture
Revision 1.3
33
3.4.2.3 Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the board.
The actual interrupt map is defined using configuration registers in the Intel
®
ICH9R.
Table 16. Interrupt Definitions
ISA Interrupt Description
INTR Processor interrupt.
NMI NMI to processor.
IRQ0 System timer
IRQ1 Keyboard interrupt.
IRQ2 Slave PIC
IRQ3 Serial port 1 interrupt from Super I/O* device, user-configurable.
IRQ4 Serial port 1 interrupt from Super I/O* device, user-configurable.
IRQ5
IRQ6 Floppy disk.
IRQ7 Generic
IRQ8_L Active low RTC interrupt.
IRQ9 SCI*
IRQ10 Generic
IRQ11 Generic
IRQ12 Mouse interrupt.
IRQ13 Floaty processor.
IRQ14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15 Secondary IDE Cable
SMI* System Management Interrupt. General purpose indicator sourced by the Intel
®
ICH9R to the
processor.
3.4.2.4 Serialized IRQ Support
The server board supports a serialized interrupt delivery mechanism. Serialized Interrupt
Requests (SERIRQ) consists of a start frame, a minimum of 17 IRQ / data channels, and a stop
frame. Any slave device in the quiet mode may initiate the start frame. While in the continuous
mode, the start frame is initiated by the host controller.
3.4.3 PCI Error Handling
The PCI bus defines two error pins, PERR# and SERR#, for reporting PCI parity errors and
system errors, respectively. In the case of PERR#, the PCI bus master has the option to retry
the offending transaction, or to report it using SERR#. All other PCI-related errors are reported
by SERR#. SERR# is routed to NMI if enabled by BIOS.