Functional Architecture Intel® Server Boards S3200SH/S3210SH TPS
Revision 1.3
20
Please note the following memory population rules:
• If dual channel operation is desired, channel A and channel B must be populated
identically (i.e., same capacity)
• Use DDR2 667/800 memory only
• The speed used on all the channels is the slowest DIMM in the system
• ECC or non-ECC DIMMs
• Can mix different memory technologies (size and density)
• Single Channel Mode (either channel may be used): DIMM slots (within the same
channel) may be populated in any order
• Dual Channel Interleaved Mode: DIMM slots may be populated in any order as long as
the total memory in each channel is the same.
• Dual Channel Asymmetric Mode: DIMM slots may be populated as one wishes (any
order)
3.2.2 PCI-X* Hub (PXH)
PXH-V: PCI-X* Hub (LX board SKU only) The PXH-V hub is a peripheral chip that performs
PCI/PCI-X* bridging functions between the PCI Express* interface and the PCI/PCI-X* bus. The
PXH-V contains two PCI bus interfaces that can be independently configured to operate in PCI
(33 or 66 MHz), PCI-X* Mode1 (66,100,133), for either 32 or 64 bits.
3.2.2.1 Segment E 64bit/133MHz PCI-X* Subsystem
One 64-bit PCI-X* bus segment is directed through the PXH-V. This PCI-X* segment (segment
E) provides the following:
• Two 3.3V 64-bit PCI-X* slots
On Segment E, PCI-X* is capable of speeds up to 133MHz operation and supports full-length
PCI and PCI-X* adapters.
3.2.2.1.1 Device IDs (IDSEL)
Each device under the PCI-X* hub bridge has its IDSEL signal connected to one bit of AD
[31:16], which acts as a chip select on the PCI-X bus segment in configuration cycles. This
determines a unique PCI-X* device ID value for use in configuration cycles. The following table
shows the bit to which each IDSEL signal is attached for P64-C devices and a corresponding
device description.
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