Intel SE7500CW2 - Extended System Configuration Data (ESCD), Plug and Play (Pnp)

SE7500CW2 Server Board Technical Product Specification System BIOS
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Revision 1.40
6.2.2.2 Processor Microcode Updates
All Intel
®
Xeon™ processors can correct specific errata by loading an Intel-supplied data block
(also called the “update”). The BIOS is responsible for storing the update in a non-volatile
memory block and loading it into each processor during the POST sequence.
The Intel Xeon processor with 512KB L2 Cache processor has the same capability for updating
the processor microcode as previous Intel processors. The SE7500CW2 server board supports
all microcode patches available for the supported processor steppings, plus an additional two
empty slots are available for updates.
6.2.3 Extended System Configuration Data (ESCD), Plug and Play (PnP)
The system BIOS supports industry standards for making the system Plug-and-Play ready.
6.2.3.1 Resource Allocation
The system BIOS identifies, allocates, and initializes resources in a manner consistent with
other Intel servers. The BIOS scans for the following, in order:
1. ISA devices: Although add-in ISA devices are not supported on these systems, some
standard PC peripherals may require ISA-style resources. Resources for these devices
are reserved as needed.
2. When the VGA add-on card is detected, the on-board VGA will be disabled automatically.
Only add-on VGA will work in such situation.
3. PCI devices: The BIOS allocates resources according to the parameters set up by the
BIOS Setup and as required by the PCI Local Bus Specification, Revision 2.1.
The system BIOS Power-on Self Test (POST) guarantees there are no resource conflicts prior
to booting the system. Note that PCI device drivers are required to support the sharing IRQs,
which should not be considered a resource conflict.
6.2.3.2 PnP ISA Auto-Configuration
The system BIOS does the following:
• Supports relevant portions of the Plug and Play ISA Specification, Revision 1.0a and the
Plug and Play BIOS Specification, Revision 1.0A.
• Assigns I/O, memory, direct memory access (DMA) channels, and IRQs from the
system resource pool to the embedded PnP Super I/O device.
• Does not support add-in PnP ISA devices.
6.2.3.3 PCI Auto-Configuration
The system BIOS supports the INT 1Ah, AH = B1h (16 bit and 32 bit mod) functions, in
conformance with the PCI Local Bus Specification, Revision 2.1. The system BIOS also
supports the 16- and 32-bit protected mode interfaces as required by the PCI BIOS
Specification, Revision 2.1.