SE7500CW2 Server Board Technical Product Specification Error Reporting and Handling
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Revision 1.40
7. Error Reporting and Handling
7.1 POST Codes, Error Messages, and Error Codes
The BIOS indicates the current testing phase during POST by writing a hex code to I/O location
80h. If errors are encountered, error messages or codes will either be displayed to the video
screen, or if an error has occurred prior to video initialization, errors will be reported through a
series of audio beep codes.
The error codes are defined by Intel and whenever possible are backward compatible with error
codes used on earlier platforms.
7.1.1 Port 80 Codes
BIOS will send a 1-byte hex code to port 80 before each task is performs.
The purpose of the port 80 codes is to provide a troubleshooting method in the event of a system
hang during the POST. Below is the table of the Port 80 codes and their corresponding task
description.
Note: Warm start only tasks are shaded, the Cold Start only tasks have heavy border.
Table 35: System ROM BIOS POST task point
Tpoint Description
02h Verify Real Mode. If the CPU is in protected mode, turn on A20 and pulse the reset line, forcing a
shutdown 0.
NOTE: Hook routine should not alter DX, which holds the power up CPU ID.
03h Disable Non-Maskable Interrupts.
04h Get CPU type from CPU registers and other methods. Save CPU type in NVRAM.
NOTE: Hook routine should not alter DX, which holds the power up CPU ID.
06h Initialize system hardware. Reset the DMA controllers, disable the videos, clear any pending interrupts
from the real-time clock and set up port B register.
07h Disable system ROM shadowed start to execute ROMEXEC code from the flash part. This task is pulled
into the build only when the ROMEXEC relocation is installed.
08h Initialize chip set registers to their initial POST values.
09h Set in-POST flag in CMOS that indicates we are in POST. This bit determines if the current configuration
causes the BIOS to hang. If so, the BIOS, on the next POST, uses default values for its configuration.
0Ah Initialize CPU registers
0Bh Enable CPU cache. Set bits in CMOS related to cache.
0Ch Set the initial POST values of the cache registers if not integrated into the chipset.
0Eh Set the initial POST values for registers in the integrated I/O chip.
0Fh Enable the local bus IDE as primary or secondary depending on other drives detected.
10h Initialize Power Management.
11h General dispatchers for alternate register initialization. Set initial POST values for other hardware
devices defined in the register tables.
12h Restore the contents of the CPU control word whenever the CPU is reset.
13h Early reset of PCI devices required to disable bus master. Assumes the presence of a stack and running
from decompressed shadow memory.
14h Verify that the 8742 keyboard controller is responding. Send a self-test command to the 8742 and wait
for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte.
16h Verify that the ROM BIOS checksums to zero
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