Error Reporting and Handling SE7500CW2 Server Board Technical Product Specification
72
Revision 1.40
Tpoint Description
17h Initialize external cache before auto-sizing memory.
18h Initialize all three of the 8254 timers. Set the clock timer (0) to binary count, mode 3 (square wave mode),
and read/write LSB then MSB. Initialize the clock timer to zero. Set the RAM refresh timer (1) to binary
count, mode 2 (Rate Generator), and read/write LSB only. Set the counter to 12H to generate the refresh
at the proper rate. Set sound timer (2) to binary count, mode 3, and read/write LSB, then MSB.
1Ah Initialize DMA command register with these settings:
1. Memory to memory disabled
2. Channel 0 hold address disabled
3. Controller enabled
4. Normal timing
5. Fixed priority
6. Late write selection
7. DREQ sense active
8. DACK sense active low.
Initialize all 8 DMA channels with these settings:
1. Single mode
2. Address increment
3. Auto initialization disabled (channel 4 - Cascade)
4,. Verify transfer
1Ch Initialize the 8259 interrupt controller with these settings:
1. ICW4 needed
2. Cascade
3. Edge-triggered mode.
20h Verify that DRAM refresh is operating by polling the refresh bit in PORTB.
22h Reset the keyboard.
24h Set segment-register addressibility to 4 GB
28h Using the table of configurations supplied by the specific chipset module, test each DRAM
configuration to see if that particular configuration is valid. Then program the chipset to its auto-sized
configuration. Before auto-sizing, disable all caches and all shadow RAM.
29h Initialize the POST Memory Manager
2Ah Zero the first 512K of RAM
2Ch Test 512K base address lines
2Eh Test first 512K of RAM.
2Fh Initialize external cache before shadowing.
32h Compute CPU speed.
33h Initialize the Phoenix Dispatch Manager
36h Vector to proper shutdown routine.
38h` Shadow the system BIOS.
3Ah Auto-size external cache and program cache size for enabling later in POST.
3Ch Set chipset registers to their CMOS values if CMOS is valid, unless auto configuration is enabled, in
which case load the chipset registers from the Setup default table.
3Dh Load alternate registers with CMOS values. Register-table pointers are in the altreg table segment.
41h Initialize extended memory for RomPilot.
42h Initialize interrupt vectors 0 thru 77h to the BIOS general interrupt handler.
45h Initialize all motherboard devices.
46h Verify the ROM copyright notice
47h Initialize support I2O by initializing global variables used by the I2O code. Paused POST table
processing if CMOS bit is set.
48h Verify that the equipment specified in the CMOS matches the hardware currently installed. If the
monitor type is set to 00 then a video ROM must exist. If the monitor type is 1 or 2 set the video switch
to CGA. If monitor type 3, set the video switch to mono. Also specify in the equipment byte that disk
drives are installed. Set appropriate status bits in CMOS or the BDA if configuration errors are found.
49h Perform these tasks:
1. Size the PCI bus topology and set bridge bus numbers.
2. Set the system max bus number.
3. Write a 0 to the command register of every PCI device.
4. Write a 0 to all 6 base registers in every PCI device.
5. Write a -1 to the status register of every PCI device.
4Ah Initialize all video adapters in system
4Bh
Initialize Quiet Boot if it is installed. Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your
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