Chapter 3 — Theory of Operation
CV30 Fixed Mount Computer Service Manual 67
The processor can set the RTC time and date as well as read the RTC time
and date over this bus.
The processor power control 12C bus is a two-wire, bi-directional, serial
bus that communicates roughly at 100 Kbps between the following devices:
• Main processor
• Processor power controller
The main processor is the master. This bus is used to change the core
processor voltage to match the clock speed of the processor. When the
processor is operating at low clock speeds, the core voltage can be reduced
to lower power consumption. When performance is required, the core
voltage is increased and then the processor clock is increased to meet the
current work load.
Client USB
The processor supports a USB1.1 client interface. This interface is routed
out to a D-Sub 15-pin connector for external connection to a PC for
ActiveSync communications. The PIC controller detects when the external
host 5 V is applied and informs the processor that the interface is active.
This signal pair is differential. Both 1.5 and 12 Mbps operation is
supported.
Host USB
The processor has a USB2.0 host interface which is connected to a USB
hub to output two USB hosts. This signal pair from the processor is
differential. Both 1.5 and 12 Mbps operation is supported.
Signal Description
SCL Serial clock for 12C
SDA Serial data for 12C
Signal Description
PWR_SCL Serial clock for 12C
PWR_SDA Serial data for 12C
Signal Description
USBC_P USB data line positive
USBC_N USB data line negative
Signal Description
USBH_P0 USB data line positive
USBH_N0 USB data line negative
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