Chapter 3 — Theory of Operation
66 CV30 Fixed Mount Computer Service Manual
SDRAM Controller
The processor contains the SDRAM controller. The SDRAM controller is
active only when the processor is active. In Sleep mode, the controller
places the SDRAM into self-refresh mode and stops operation. Note that
the processor must apply the SDRAM row and address lines on the Address
bus plus use this bus for normal operation.
General Purpose IO
The processor has multiple functions for the GPIOs. When the special
functions are not utilized, these pins have a variety of general purpose uses
to control or sense the hardware.
12C Bus
There are two different 12C bus implementations in this product:
• Processor general purpose 12C bus
• Processor power control 12C bus
For more information on the connection of the 12C bus, refer to the
“Main Processor Functional Diagram” on page 65.
The processor general purpose 12C bus is a two-wire, bi-directional, serial
bus that communicates roughly at 100 Kbps between the following devices:
• Main processor
• PIC controller
• Real time clock
The main processor is the master and all other devices are slaves. Only one
device on this bus can communicate at a time. The protocol looks for
collisions and retries if they are detected. The main processor sends
commands to the PIC controller to execute and the PIC sends results or
responses back to the main processor over this bus.
SDRAM Controller Description
SDRAM Signal Description
SDCKE_1 SDRAM clock enable
SDCLK_0 SDRAM clock
SDCLK_0 SDRAM clock
nSDRAS SDRAM row address strobe
nSDCAS SDRAM column address strobe
DQM_0 SDRAM data byte path
DQM_1 SDRAM data byte path
DQM_2 SDRAM data byte path
DQM_3 SDRAM data byte path
nSDCS_0 Chip select used for 64 MB or less
nSDCS_1 Chip select used fro 64 MB to 128 MB
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