LD1 Blue Station port in use status
ON: a station port is in use
OFF: All station ports are idle
LD2 Blue ON: a BRI line in use
LD3 Red ON: BRI Line Error, BRI 1 or 2
OFF: both BRI lines normal
LD4 Blue ON: BRI reference clock external
OFF: BRI reference clock internal
4.7.6 PRIU (1 PRI -30 Channels- Interface Board)
The PRIU board provides a standard PRI or E1 interface circuit. The PRIU, as shown in
Description
Figure 4.7.6-1, can be installed only on the CN2 connector of either an MBUI or MBUID.
The interface circuit complies with ITU-T Recommendations G.704, G.703 and G.823. The
PRIU employs the CEPT frame format, which consist of 32, 8-bit time slots at a data rate of
2.048MHz. The time slot TS 0 is allocated to frame alignment, time slot TS 16 is allocated
as the signaling channel, and the other 30 time slots are available as Bearer ‘B’ channels.
The PRIU circuit will extract the reference clock from the incoming PRI circuit. The
extracted clock is sent to the PLL circuitry of the MBU to synchronize the main clocks. The
PRIU can operate in the TE slave or NT master mode.
The PRIU supports pulse dialing, DTMF dialing, and MFC-R2 register signaling (based on
ITU-T Recommendation Q.440-480).
A multiple pole Dip-switch determines the type of interface circuit, PRI or E1. The TE and
NT operating mode is determined through database configuration.
To install the board in the KSU, refer to section 4.4.
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