Programming Guide – 54
Status Byte Register
The status byte register contains the summary bits for each of the structures implemented in
the attenuator and either the master summary bit (MSB) or the request for service bit (RQS).
Status Byte Register
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
not
used
not
used
not
used
questionable
summary
(QSB)
message
available
(MAV)
event
summary
(ESB)
request for
service
or
master
summary
operation
summary
(OSB)
Read with
Serial polling
*STB?
Written to with
Cannot be written to
Cleared by
*CLS common command
• Bit 0 is not used.
• Bit 1 is not used.
• Bit 2 is not used.
• Bit 3 (questionable summary) is the summary bit for questionable status structure. It is set if
any bit in the questionable event status register is set while the corresponding bit in the
questionable event enable register is set.
• Bit 4 (message available) is set to 1 when a response message is available in the output
queue.
• Bit 5 (event summary bit) is the summary bit for the standard event status structure. The
ESB summary message bit is set if any bit in the standard event status register is set while
its corresponding in the standard event status enable register is set.
• Bit 6, as the service request bit, is set to 1 if a service request has been generated. The
SRQ bit is set internally and is not visible to the user.
Bit 6, as the master summary bit, is set if there is at least one reason for the attenuator to
request service from the controller. That is, the master summary bit is set if any summary
bit in the status byte register is set and if the corresponding bit in the service request
enable register is also set. The MSB is returned as bit 6 when the status register is queried
or the attenuator is serial polled.
• Bit 7 (operation summary bit) is the summary bit for the operation status register. It is set if
any bit in the operation event register is set while the corresponding bit in the operation
event enable register is set.
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