Each counter (Counter0 or Counter1) consists of a 32-bit register that accumulates the number
of falling edges detected on the external pin. If a counter is reset and read in the
same function
all, the read returns the value just before the reset.
he timers (Timer0-Timer1) have various modes available:
for the timer base clock:
pply to the U3 hardware revision 1.21. With hardware revision 1.20 all
fixed frequency, and are not affected by TimerClockDivisor. The
n be further adjusted by TimerClockDivisor, but when using
ese clocks Counter0 is not available. When Counter0 is not available, it does not use an
ote that the DACs (Section 2.x) are derived from PWM signals that are affected by the timer
ts in
c
T
Timer Modes
0 16-bit PWM output
Both timers use the same timer clock. There are 7 choices
1 8-bit PWM output
3 Period input (32-bit, falling edges)
4 Duty cycle input
5 Firmware counter input
6 Firmware counter input (with debounce)
7 Frequency output
8 Quadrature input
9 Timer stop input (odd timers only)
10
System timer low read
(default mode)
11 System timer high read
12 Period input (16-bit, rising edges)
13 Period input (16-bit, falling edges)
TimerBaseClock
2 Period input (32-bit, rising edges)
04 MHz
112 MHz
4 4 MHz /Divisor
5 12 MHz /Divisor
6 48 MHz /Divisor
2 48 MHz (Default)
3 1 MHz /Divisor
Note that these clocks a
clocks are half of the values above.
The first 3 clocks have a
frequency of the last 4 clocks ca
th
external FIO/EIO pin.
N
clock frequency. The default timer clock frequency of the U3 is set to 48 MHz, as this resul
the minimum DAC output noise. If the frequency is lowered, the DACs will have more noise,
where the frequency of the noise is the timer clock frequency divided by 2
8
.
31
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